Main Board Revisions

Main Board Revisions, Notes

20130507

Known Issues and Concerns

• Protection on DC jack input for overvoltage or reverse polarity?
• I2C pinning on FPGA complains about an output too close to a VREF pin. Move the I2C pins elsewhere?
• DDR2 interface is untested.
• Fix footprint alignment problem for DDR2 socket. Pay attention to "D3" and "D4" measurements on datasheet, which establish a stagger between the rows of pins on each side of the connector.
• Microcontroller SWD connector numbering is mirrored. Do not follow Sullins' pin numbering scheme!
• FPGA JTAG connector numbering is mirrored. Do not follow Sullins' pin numbering scheme!
• Look at using a boost/buck switcher to replace VRAW with +5V regulated. Would provide better VUSB regulation to hosted USB devices, allow a wider range of DC adapter voltages to be used. Might enable use with a lithium or other ~3.5V batteries.
• Open up the V1P8 switcher component placement a bit for easier hand-soldering?
• Improve connector for FPGA JTAG?
• Use 2.1mm ID DC jack, since 2.5mm seems more uncommon, and not necessarily correlated to higher-current DC adapters? Marshallh recommends: http://www.digikey.com/product-detail/en/PJ-051AH/CP-051AH-ND/1644587, but this requires plated slots. Instead, I am making a BOM-only change to the CUI PJ-102AH.
• Expose TUSB1310A JTAG pins as test points, at least?
• Fiducials for major components, for mass assembly, if necessary?
• Silkscreen reference designators, just to be helpful?
• Check out silkscreen outlines on some resistors on the back side, which seem to be missing.
• Figure out why MIC5207 ADJ caps seem to cause low-level (~100mV, ~22kHz) oscillations on the regulated output.
• Add LEDs to FPGA outputs! Entertain using LED-oriented transistor packages like those used on the BeagleBone Black (DMC56404) to get around voltage/drive complications.
• Renumber clock/input-only pins on front end banks to not be a generic number on the schematic.
• Find room for a 2x5 0.1" USB Blaster JTAG connector. See USB-Blaster Download Cable User Guide for more details.
• Swap RX and TX pairs on the USB 3.0 SS connector. Pay heed to USB 3.0 ECN 17, and do not trust table 5-6, or the USB3120 datasheet, which apparently copied the erroneous table 5-6 from the USB spec.
• Make more room along right edge of board for the -GP and -RT1 variants of the QTH/QSH connectors. At present, there's a conflict with one of the mounting holes. It might make more sense to move the mounting hole, or to shift the board outline 2mm or 3mm to the right, especially if room can be reclaimed by moving the USB 3.0 connector to the other side and fixing the TX/RX pair problem -- more direct routing for all USB-related signals.
• Fatten up U8 (TPS2113A) priority voltage switch to support 3A, so that 2A can be supplied to two USB 3.0 ports on a front-end, and 1A can be used by the main board and other front-end hardware.
• Adjust power path components to support 6VDC input on DC jack. Most components are fine with 6V, but there's one or two that aren't (5.5V Absolute Maximum).
• Consider throwing a buck switcher (maybe the one on the USB FE?) after the DC jack to regulate any supply >=5.5V down to 5V. Since there's precious little power from the main board USB 3.0 connector, any serious power will need to come from the DC jack either on the main board or on the FE.
• Put reverse polarity protection on DC jacks. See Terasic DE1-SoC schematic for an example implementation.