Front End Implementation How To

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To implement a front end board, you must:

• Place an I2C EEPROM on your front end board (memory size and I2C address TBD), used to identify the front end board and load the correct FPGA bitstream. This I2C EEPROM will be the ONLY device on your front end board that is powered from the FE_I2C_VCC signal. The FE_I2C_SCL and FE_I2C_SDA signals connect to the I2C interface on the I2C EEPROM. Pull-up resistors for the SCL and SDA signals are not necessary, as they are provided on the main board. This I2C bus is shared with the main board clock generator (Si5351C-B) and DDR2 RAM I2C, so be aware of potential I2C address conflicts. The FE_I2C_VCC signal is 3.3 Volts, and is present whenever the main board is connected to power.
• Regulate all power necessary for your front end (except the I2C EEPROM, see above) from the VRAW_SW signals. This voltage will be between approximately 4.5V and 6V, depending on whether main board power is sourced from USB 3.0 (nominally 5V @ 900mA), the main board DC jack (5V or 6V, up to 2A), or a DC jack or other power source on your front end board. Use ALL four of the VRAW_SW signals, to maximize current capacity between the main board and front end.
• Power the FE_VCCIO_[ABC] signals with the voltages you want each bank to use as a reference for signals. Ensure that all three banks are powered immediately upon startup. For instance, if you want to transact signals on bank A with 3.3V CMOS levels, power the FE_VCCIO_A signals with 3.3V. If you want bank C to use 1.8V signaling, power the FE_VCCIO_C signals with 1.8V. Note that the FPGA can often support multiple input signal levels for a given VCCIO voltage, which can help when you want to send two different types of signals (e.g. 3.3V and 2.5V) over the same bank. Consult the Cyclone 4 Handbook, Volume 1, Section 6 "I/O Standards" for more information.
• Connect VALT_FE through a 10k resistor to VRAW_SW. This is required so that the mainboard can detect the presence of the front-end module.
• Send clocks from your front end on suitable FPGA signals. Some FE_[ABC]* signals connect to FPGA clock inputs (CLK or DIFFCLK_[np]), which are preferred for sending clocks to the FPGA, as these inputs minimize clock skew and connect intimately with the FPGA's onboard PLL hardware. These are pins 56, 58, 103, 105, 145, and 147 on the mezzanine connector. Avoid these pins for other uses. Consult the Cyclone 4 Handbook, Volume 1, Section 6 "Clock Pins Functionality" for more information.

Optionally you may:

• Match signal lengths in your design. The Daisho main board doesn't particularly attempt to match lengths. Matching was de-prioritized due to the large number of signals to the mezzanine connector, the size constraints of the main board PCB, density of routing between the FPGA and mezzanine connector, and the wide disparity in distances between the FPGA pins and mezzanine pins. It was thought that keeping signal integrity high and propagation delay low was best for a general-purpose high-speed interface, and that individual modules can solve the matching problem to the extent they need to.
• Use the FE_CLK_[PN][01] clock signals from the main board clock generator. This is good if you need a high-quality reference frequency controlled by the FPGA or microcontroller, or several related clocks. These clock signals are 3.3V CMOS, but can be divided (via a resistive or capacitive voltage divider) to achieve other voltage swings. You can source clocks on your front end board, via crystals or oscillators if you don't need the special services of the main board clock generator.
• Send a reference signal to the main board clock generator via FE_CLKSRC, if you need to derive many related clocks from a clock on your front end. This clock is referenced to a 3.3V supply.
• Provide a 5 to 6 V power supply to the mainboard on VALT_FE.