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Main Board Hardware Details
Hardware details of the Daisho main board design. Definitely a work in progress. Please add questions and ideas as they occur.
Altera EP4CE30F29C in a 780-pin BGA package.
Front end boards with two interfaces will often provide two clocks (one for each interface) running either at different clock speeds, or from the same clock reference but with different phases. This requires two of the FPGA PLLs. And each PLL is directly accessible from only one side of the FPGA. So the front end connector must provide PLL clock inputs from two sides of the FPGA to minimize jitter induced by FPGA routing.
VCCIO = 3.3V. Configuration and miscellaneous control signals.
VCCIO = 1.8V. Configuration signals, mostly to front-end board. In future revisions, transceivers in this bank may deliver differential pairs to the front-end connector. This bank has its own LDO regulator, set to 1.2V, adjusted upward by a resistor on the front-end board.
VCCIO = 1.8V. Interface to DDR2 SO-DIMM socket, using DQ/DQS/DM dedicated pins for data/strobe signals, and miscellaneous pins for address/configuration/status.
Bank 5 will share signals with the onboard USB 3.0 interface, primarily slow signals like ULPI and configuration/status.
VCCIO = 1.8V. High-speed (PIPE RX and TX) interfaces to onboard USB 3.0 PHY. Assorted USB 3.0 configuration/status signals, which should minimize simultaneous switching output (SSO) signal integrity issues (vs. putting ULPI in this bank -- though I suppose ULPI and PIPE will not operate simultaneously?).
VCCIO = 1.8V default, or front-end controlled. High-speed signals, kept in differential pairs where possible, kept to a bank on the front-end connector. This bank has its own LDO regulator, set to 1.2V, adjusted upward by a resistor on the front-end board.
VCCIO = 1.8V default, or front-end controlled. High-speed signals, kept in differential pairs where possible, kept to a bank on the front-end connector. This bank has its own LDO regulator, set to 1.2V, adjusted upward by a resistor on the front-end board.
Bitstreams are loaded through the main board microcontroller, from a micro SD card. FPGA is configured via passive serial (PS) bitstream loading. No other configuration modes are supported, as no effort is being made to wire up signals for other configuration options. JTAG signals are connected to the microcontroller, so JTAG bitstream control is also supported. JTAG does not require modification to the configuration mode signals, so the configuration mode signals are hard-wired.
The main board has one USB 3.0 "SuperSpeed" interface, implemented by a TI TUSB1310A, connected to the FPGA. Both the ULPI (USB 2.0 LS/FS/HS) and PIPE (USB 3.0 SS) interfaces are supported.
Support for OTG and Host mode is desired on the main board USB interface. The type A connector was entertained, but would prevent USB LS/FS/HS support and sourcing power from a host using an A-A cable. (A-A cables do not connect VBUS or D+/D-.)
A micro-AB connector was found that supports through-hole mechanical support.
The TUSB1310A receives its reference clock via a crystal, but may be optionally configured to run from an Si5351 clock output or an oscillator. An oscillator is assumed impractical because of the jitter requirements and expense and power requirements of a low-jitter oscillator.
The TUSB1310A errata recommends using a 40MHz reference clock if the spread-spectrum clocking feature is used. A higher clock speed is also preferred to lower jitter due to noise induced into the clock signal. Since the FPGA will ultimately synchronize with the PLL output from the TUSB1310A (which will be at unknown phase relative to the reference clock), there's little point in trying to source the USB 3.0 reference clock off of some common FPGA/clock generator source. The indeterminate USB 3.0 interface clocks will require unique clock domains inside the FPGA, which should not be a significant challenge.
Samtec QTH/QSH in the 90-position, single-ended configuration (QTH-090-01-F-D-A and QSH-090-01-F-D-A). These provide 180 signals plus ground plane between the two boards. The QTH/QSH connectors are arranged in banks of 30 positions (60 signals). So the 090 part provides three banks.
The QTH connector appears to be more mechanically-robust, so it is the connector used on the main board. The QSH connector is used on front-end board, which are assumed to be less valuable than the main board. So it is desirable if a connector wears out, for it to be on the front-end side. But front-ends will see 1/n cycles (assuming "n" front-end boards being used equally), so it may all balance out anyway...
The connectors come in several varieties. The connector footprints are designed to support each of these options.
Power and configuration, plus differential pairs for clocks or high-speed serial interfaces. These differential pairs match the configuration of the -DP variety of the selected connector.
Signals from one bank of the FPGA. VCCIO used on this bank is controlled from the front-end. Signals are kept in differential pairs where possible. Applications using single-ended buses will group directional signals on one row of pins or the other, to improve signal integrity a bit.
Signals from one bank of the FPGA. VCCIO used on this bank is controlled from the front-end. Signals are kept in differential pairs where possible. Applications using single-ended buses will group directional signals on one row of pins or the other, to improve signal integrity a bit.
Goal is to get the main board design into ~100mm square (or 4", if you're clinging to imperial units).
Front-end boards will be the same dimensions as the main board. Stand-offs will prevent front-end/main board contact, and provide guides for the front-end to minimize damage to the front-end/main board connectors.
It's assumed the stack will be used with the front-end facing up, for easy observation of the target connectors and front-end status indicators.
Effort will be made to put most or all of the connectors and indicators along one edge of the stack.
Bitstream configuration occurs via an onboard microcontroller with a micro SD card. The microcontroller is from the NXP LPC11Uxx series. The microcontroller's USB interface is exposed via a USB micro B connector. SD card interface is via basic SPI, as there is no SDIO peripheral on the chosen microcontroller. The microcontroller implements a FAT filesystem using the FatFs library. The microcontroller implements some sort of USB interface to command the loading of different bitstreams, so that the SD card does not need to be removed or otherwise manipulted. The microcontroller may implement a USB mass storage device for loading directly over the microcontroller USB interface. A JTAG protocol may also be supported for direct JTAG programming of the FPGA, without involvement of the micro SD card. An ARM-standard, 10-pin 0.050" JTAG/SWD connector is provided for microcontroller software development and debugging.
The microcontroller has an I2C connection to the front-end board, which will typically be connected to an identification EEPROM. The microcontroller reads the front-end identification in order to select a default bitstream to load from the SD card. The SD card socket has an insertion detect feature that restarts the front-end identification and bitstream loading process, which allows the user to conveniently switch bitstreams for a given front-end board, simply by inserting a different SD card.
There are three power sources on the main board: USB voltage (VUSB), a power connector on the main board (VMB), or power from the front end board (VFE). The voltage from any of these sources is required to be 4.4 V or higher.
The unregulated sources are selected using Schottky diodes to OR the sources together. Assume 0.5V loss maximum across the diode in the path of the active source.
From the unregulated power source (3.9V to 4.7V, 900mA maximum), power is regulated and distributed thusly:
TODO: Consider swapping TPS624xx channels, or upgrade switcher to support 2.0A on 1.8V channel?
- FET to front end, microcontroller-activated
- Switcher down to 3.3 V (90% efficient: 3.16W/0.95A max, TPS62420: 1.0A limit)
- FET to front end, microcontroller-activated
- Microcontroller
- SD Card
- FPGA VCCIO1 (config)
- DDR2 VDDSPD (3mA max)
- USB VDDA3P3 (13mW)
- Clock Generator VDD
- Clock Generator VDDI2C
- Clock Generator VDDOA
- Clock Generator VDDOB
- LDO to 2.5 V
- FPGA VCCA
- Switcher down to 1.8 V (90% efficient: 3.16W/1.75A max, TPS62420: 0.6A limit)
- FET to front end, microcontroller-activated
- FPGA VCCIO3 (DDR2)
- FPGA VCCIO4 (DDR2)
- FPGA VCCIO5 (DDR2, USB)
- FPGA VCCIO6 (USB)
- DDR2 VDD (700mA typical @ 133MHz, extrapolated from 2GByte Micron SODIMM across 1GHz/800MHz/667MHz specs. 200mA max during self-refresh -- not clock dependent.)
- DDR2 VDDQ
- USB VDD1P8 (128mW/71mA typical)
- USB VDDA1P8 (77mW/43mA typical)
- LDO to 1.2 V (??? typical, 0.6V drop = ??? loss)
- FPGA VCCINT
- FPGA VCCD_PLL
- FPGA VCCIO2 (if front end not powered, microcontroller-activated)
- FPGA VCCIO7 (if front end not powered, microcontroller-activated)
- FPGA VCCIO8 (if front end not powered, microcontroller-activated)
- LDO to 1.1 V (220mW/200mA typical, 0.7V drop = 140mW loss)
- USB VDD1P1 (98mW/89mA typical)
- USB VDDA1P1 (118mW/107mA typical)
TODO: Clock generator VDDOC and VDDOD are under control of the front end?
- 1V2: VCCINT, VCCD_PLL
- 1V8: Bank 3/4 (DDR2), Bank 5 (DDR2/USB3), Bank 6 (USB3)
- 2V5: VCCA
- 3V3: Bank 1 (configuration, requires 3V3, 3V0, or 2V5)
VCCIOs for banks connected to the front end are controlled by the front end. If no front end board is attached, the VCCIOs must be at a valid voltage. (Cyclone IV datasheet, table 1-3: "VCCIO for all I/O banks must be powered up during device operation.") So, use a diode from 1V2 supply, with < 0.05V drop at 10mA (assuming no activity on bank) to meet bank VCCIO requirements. Because of the voltage drop as current increases, front-end boards should not rely on this mechanism to supply 1V2 VCCIO, and should take responsibility for powering VCCIO at 1V2. However, there is also an Altera knowledge base article that suggests only configuration banks need VCCIO in the recommended range, as it's required to leave power-on reset. There is a foreboding comment about Altera not characterizing devices in the VCCIO=0 state, however.
It might be easier just to gate all supplies to the front-end and have a pseudo hot-plug arrangement. Supplies are gated by FETs controlled by the microcontroller. Front-end sources VCCIOs that it sends back through the connector. FETs also gate the default 1V2 supply onto the front-end VCCIOs, but are activated exclusively to the front-end power supply.
- 1V1: VDD1P1, VDDA1P1 (216mW typical)
- 1V8: VDD1P8, VDDA1P8 (205mW typical)
- 3V3: VDDA3P3 (13mW typical)
- 1V8: VDD, VDDQ
- 0V9: VREF (reference voltage, very low loading, may be voltage divider?)
- 1V8 - 3V3: VDDSPD. Optional temperature sensor support may be dependent on certain VDDSPD voltage sub-range, which appears to be 3V0 - 3V6. So prefer 3V3? Also makes hooking up to microcontroller SPI easier...
- 2V5 or 3V3: Core
- 1V8, 2V5, or 3V3: Output drivers (under control of front-end board?)
- 3V3: LPC11U14 (requires 1V8 - 3V6)
- 3V3: SD card (requires 2V7 - 3V6)
TODO:
Prototypes use the Sunstone six-layer quickturn process. The layer stack is:
- Layer 1: 1.7 mil copper (0.5 oz foil, plated)
- 6.4 mil Er 4.5 (1 x 2116, 1 x 1080)
- Layer 2: 1.4 mil copper (1.0 oz)
- 14.0 mil Er 4.5 (laminate)
- Layer 3: 1.4 mil copper (1.0 oz)
- 8.4 mil Er 4.5 (2 x 2116)
- Layer 4: 1.4 mil copper (1.0 oz)
- 14.0 mil Er 4.5 (laminate)
- Layer 5: 1.4 mil copper (1.0 oz)
- 6.4 mil Er 4.5 (1 x 2116, 1 x 1080)
- Layer 6: 1.7 mil copper (0.5 oz foil, plated)
Layer 2 is Ground. Layer 5 is power. The distance between planes is 39.2 mils (1mm). Capacitance between power and ground planes is estimated at 25.8pF per square inch, or 4pF per square centimeter.
Using ATLC to estimate layer characteristics:
- Microstrip (top and bottom layers) of 50 Ohms: 0.265 mm trace, 49.8 Ohms, 118 pF/meter, 294 nH/meter, 5.89 ns/meter (5.89 ps/mm, 150 ps/inch).
- Stripline (inner layers) of 50 Ohms: 0.345 mm trace, 50.0 Ohms, 141 pF/meter, 354 nH/meter, 7.08 ns/meter (7.08 ps/mm, 180 ps/inch).
To be determined... But likely to include a 4.4 mil spacing between top/bottom and ground/power planes. With no edge-card connector requirement now, a 32 mil PCB may also be possible, which would provide thinner controlled impedance traces.