Add GPU project chipyard changes

.gitmodules

@@ -48,7 +48,7 @@
 	url = https://github.com/ucb-bar/rocc-acc-utils.git
 [submodule "generators/rocket-chip"]
 	path = generators/rocket-chip
-	url = https://github.com/chipsalliance/rocket-chip.git
+	url = https://github.com/richardyrh/rocket-chip.git
 [submodule "generators/rocket-chip-blocks"]
 	path = generators/rocket-chip-blocks
 	url = https://github.com/chipsalliance/rocket-chip-blocks.git
@@ -151,3 +151,6 @@
 [submodule "generators/vexiiriscv"]
 	path = generators/vexiiriscv
 	url = https://github.com/ucb-bar/vexiiriscv-tile.git
+[submodule "generators/radiance"]
+	path = generators/radiance
+	url = https://github.com/ucb-bar/radiance.git

build.sbt

@@ -156,7 +156,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
 lazy val chipyard = (project in file("generators/chipyard"))
   .dependsOn(testchipip, rocketchip, boom, rocketchip_blocks, rocketchip_inclusive_cache,
     dsptools, rocket_dsp_utils,
-    gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+    radiance, gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
     compressacc, saturn, ara, firrtl2_bridge, vexiiriscv)
   .settings(libraryDependencies ++= rocketLibDeps.value)
@@ -243,6 +243,17 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val radiance = (project in file("generators/radiance"))
+  .dependsOn(rocketchip, gemmini)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(libraryDependencies ++= Seq(
+      "edu.berkeley.cs" %% "chiseltest" % chiselTestVersion,
+      "org.scalatest" %% "scalatest" % "3.2.+" % "test",
+      "junit" % "junit" % "4.13" % "test",
+      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
+  ))
+  .settings(commonSettings)
+
 lazy val gemmini = freshProject("gemmini", file("generators/gemmini"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)

common.mk

@@ -16,6 +16,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_LDFLAGS         = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
+"   EXTRA_SIM_OUT_NAME        = additional suffix appended to the simulation .out log filename" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
 "   MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \
@@ -26,6 +27,7 @@ EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
 EXTRA_SIM_REQS       ?=
+EXTRA_SIM_OUT_NAME   ?=
 
 ifneq ($(ASPECTS), )
 	comma = ,
@@ -67,6 +69,7 @@ include $(base_dir)/generators/ibex/ibex.mk
 include $(base_dir)/generators/ara/ara.mk
 include $(base_dir)/generators/tracegen/tracegen.mk
 include $(base_dir)/generators/nvdla/nvdla.mk
+include $(base_dir)/generators/radiance/radiance.mk
 include $(base_dir)/tools/torture.mk
 
 #########################################################################################
@@ -233,6 +236,8 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &:  $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
 		--model-module-name $(MODEL) \
 		--out-dut-smems-conf $(TOP_SMEMS_CONF) \
 		--out-model-smems-conf $(MODEL_SMEMS_CONF)
+#	for blackboxed SRAMs: define mem here and use generated module name in blackbox source
+	-[ -f $(base_dir)/vlsi/add.mem.conf ] && cat $(base_dir)/vlsi/add.mems.conf >> $(TOP_SMEMS_CONF)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 TOP_MACROCOMPILER_MODE ?= --mode synflops
@@ -305,15 +310,15 @@ get_loadarch_flag = +loadarch=$(subst mem.elf,loadarch,$(1))
 endif
 
 # get the output path base name for simulation outputs, First arg is the binary
-get_sim_out_name = $(output_dir)/$(call get_out_name,$(1))
+get_sim_out_name = $(output_dir)/$(call get_out_name,$(1))$(if $(EXTRA_SIM_OUT_NAME),.$(EXTRA_SIM_OUT_NAME),)
 # sim flags that are common to run-binary/run-binary-fast/run-binary-debug
 get_common_sim_flags = $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(call get_loadmem_flag,$(1)) $(call get_loadarch_flag,$(1))
 
 .PHONY: %.run %.run.debug %.run.fast
 
 # run normal binary with hardware-logged insn dissassembly
 run-binary: check-binary $(BINARY).run
-run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
+run-binaries: check-binaries $(addsuffix .run,$(wildcard $(BINARIES)))
 
 %.run: %.check-exists $(SIM_PREREQ) | $(output_dir)
 	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
@@ -327,7 +332,7 @@ run-binaries: check-binaries $(addsuffix .run,$(BINARIES))
 
 # run simulator as fast as possible (no insn disassembly)
 run-binary-fast: check-binary $(BINARY).run.fast
-run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
+run-binaries-fast: check-binaries $(addsuffix .run.fast,$(wildcard $(BINARIES)))
 
 %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir)
 	(set -o pipefail && $(NUMA_PREFIX) $(sim) \
@@ -340,7 +345,9 @@ run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES))
 
 # run simulator with as much debug info as possible
 run-binary-debug: check-binary $(BINARY).run.debug
-run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))
+run-binary-debug-bg: check-binary $(BINARY).run.debug.bg
+run-binaries-debug: check-binaries $(addsuffix .run.debug,$(wildcard $(BINARIES)))
+run-binaries-debug-bg: check-binaries $(addsuffix .run.debug.bg,$(wildcard $(BINARIES)))
 
 %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
 ifeq (1,$(DUMP_BINARY))
@@ -356,6 +363,19 @@ endif
 		$(BINARY_ARGS) \
 		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)
 
+%.run.debug.bg: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
+	if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
+	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \
+		$(PERMISSIVE_ON) \
+		$(call get_common_sim_flags,$*) \
+		$(VERBOSE_FLAGS) \
+		$(call get_waveform_flag,$(call get_sim_out_name,$*)) \
+		$(PERMISSIVE_OFF) \
+		$* \
+		$(BINARY_ARGS) \
+		</dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) >$(call get_sim_out_name,$*).log \
+		& echo "PID=$$!")
+
 run-fast: run-asm-tests-fast run-bmark-tests-fast
 
 #########################################################################################

conda-reqs/chipyard-extended.yaml

@@ -46,6 +46,9 @@ dependencies:
     - findutils
     - lzop
 
+    # dpi module
+    - rust
+
     - bash-completion
     - ca-certificates
     - mosh

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -29,6 +29,8 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
   with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
+  with radiance.memory.CanHaveMemtraceCore // Enables memtrace core
+  with radiance.memory.CanHaveRadianceROMs // Enables radiance argument ROMs
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
   with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
   with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget