Added Tests and Coverage for Exception Handling(Illegal instruction, environment calls and misaligned address exceptions) and Trap State Restoration Exceptions

coverage/excp_msu/rv32i_excp_Mmode.cfg

@@ -0,0 +1,53 @@
+
+                                         # Address illegal instruction exceptions coverpoints #
+
+# This coverpoint will cover the illegal csr inappropriate csr and read only csr accesses, causing illegal instruction exceptions
+cp_M_excp_illegal:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    "{csrrw, csrrs, csrrc, ecall}": 0
+  val_comb:
+  # for illegal csr
+    mode ==  'M' and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0
+
+  # for inappropriate csr
+    mode ==  'M' and mnemonic == "csrrs" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # for read only csr
+    mode ==  'M' and mnemonic == "csrrc" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # When mstatus TVM bit is set, accessing satp and sfence.vma in M-Mode should not raise illegal instruction fault.
+    mode == "M" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and satp != 0: 0
+
+
+
+                                # Address misaligned exceptions coverpoints #
+
+# coverpoint for the load address misaligned
+cp_M_load_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    lw : 0
+  val_comb:
+    mode == 'M' and mnemonic == "lw" and mcause == ${CAUSE_MISALIGNED_LOAD} : 0
+
+# coverpoint for the store address misaligned
+cp_M_store_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    sw : 0
+  val_comb:
+    mode == 'M' and mnemonic == "sw" and mcause == ${CAUSE_MISALIGNED_STORE} : 0
+
+# this coverpoint is for ecall in machine mode  
+cp_M_ecall:
+  config: 
+    - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
+  mnemonics: 
+    ecall: 0
+  val_comb:
+  # for ecall
+    mode ==  'M' and mnemonic == "ecall" and mcause == ${CAUSE_MACHINE_ECALL} : 0

coverage/excp_msu/rv32i_excp_Smode.cfg

@@ -0,0 +1,61 @@
+
+                                                  # Coverpoints for S mode #
+
+# this coverpoint is for ecall in Supervisor mode  
+cp_S_ecall:
+  config: 
+    - check ISA:=regex(.*32.*); ISA:=regex(.*I.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+  mnemonics: 
+    ecall: 0
+  val_comb:
+  # for ecall
+    mode ==  'S' and mnemonic == "ecall" and mcause == ${CAUSE_SUPERVISOR_ECALL} : 0
+
+
+                                           # Illegal instruction exceptions coverpoints #
+
+# This coverpoint will cover the illegal csr inappropriate csr and read only csr accesses, causing illegal instruction exceptions
+cp_S_excp_illegal:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+
+  mnemonics:
+    "{csrrw, csrrs, csrrc, ecall}": 0
+
+  val_comb:
+  # for illegal csr
+    mode ==  'S' and mnemonic == "csrrc" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0
+
+  # for inappropriate csr
+    mode ==  'S' and mnemonic == "csrrs" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # for read only csr
+    mode ==  'S' and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # for mstatus_tvm bit enable
+    mode == "S" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0
+
+
+
+
+                                  # Address misaligned exceptions coverpoints #
+
+# coverpoint for the load address misaligned
+cp_S_load_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_mtrap_routine=True
+  mnemonics:
+    lw : 0
+  val_comb:
+    mode == 'S' and mnemonic == "lw" and mcause == ${CAUSE_MISALIGNED_LOAD} : 0
+
+# coverpoint for the store address misaligned
+cp_S_store_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    sw : 0
+  val_comb:
+    mode == 'S' and mnemonic == "sw" and mcause == ${CAUSE_MISALIGNED_STORE} : 0
+
+

coverage/excp_msu/rv32i_excp_Umode.cfg

@@ -0,0 +1,67 @@
+
+
+
+# this coverpoint is for ecall in Supervisor mode  
+cp_U_ecall:
+  config: 
+    - check ISA:=regex(.*32.*); ISA:=regex(.*I.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+
+  mnemonics: 
+    ecall: 0
+
+  val_comb:
+  # for ecall
+    mode ==  'U' and mnemonic == "ecall" and mcause == ${CAUSE_USER_ECALL}: 0
+
+cp_U_excp_illegal:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+
+  mnemonics:
+    "{csrrw, csrrs, csrrc, ecall}": 0
+
+  val_comb:
+  # for illegal csr/ non existing csr
+    mode ==  'U' and mnemonic == "csrrc" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0  
+
+  # for inappropriate privillage mode
+    mode ==  'U' and mnemonic == "csrrs" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0
+
+  # for writing read only register
+    mode ==  'U' and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0
+
+  # for mstatus_tvm bit enable
+    mode == "U" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION}: 0
+
+  # for medeleg
+    mode == "U" and (medeleg == 0x100) and mnemonic == "ecall" and scause == ${CAUSE_USER_ECALL}: 0
+
+
+                      # coverpoint for the load address misaligned #
+
+cp_U_load_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+
+  mnemonics:
+    lw: 0
+
+  val_comb:
+  # for load
+    mode ==  'U' and mnemonic == "lw" and mcause == ${CAUSE_MISALIGNED_LOAD} : 0  
+
+                      # coverpoint for the load address misaligned #
+
+cp_U_store_addr_misaligned:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True
+
+  mnemonics:
+    sw: 0
+
+  val_comb:
+  # for store
+    mode ==  'U' and mnemonic == "sw" and mcause == ${CAUSE_MISALIGNED_STORE} : 0 
+
+
+

coverage/excp_msu/rv32i_traps_entry.cfg

@@ -0,0 +1,147 @@
+
+                  # These coverpoints will check that when illegal instrction exception occrs 
+                  # does it correctly updates the valuse of the mcause and mtval                        
+
+
+m_trap_test_illegal_m_cause_tval:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    csrrw : 0
+  val_comb:
+  # for illegal csr
+    mode ==  'M' and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} and mtval == 0xfff31073 : 0
+
+s_trap_test_illegal_m_cause_tval:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    csrrc : 0
+  val_comb:
+  # for illegal csr
+    mode ==  'S' and mnemonic == "csrrc" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} and mtval == 0xfff73373 : 0    
+
+u_trap_test_illegal_m_cause_tval:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    csrrs : 0
+  val_comb:
+  # for illegal csr
+    mode ==  'U' and mnemonic == "csrrs" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} and mtval == 0xfff72373 : 0    
+
+
+                   # These coverpoints will check that when illegal instrction exception occurs 
+                   # does it correctly updates the values of the scause and stval
+
+s_trap_test_illegal_s_cause_tval:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    csrrc : 0
+  val_comb:
+  # for illegal csr
+    mode ==  'S' and mnemonic == "csrrc" and scause == ${CAUSE_ILLEGAL_INSTRUCTION} and stval == 0xfff73373 : 0    
+
+u_trap_test_illegal_s_cause_tval:   
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    csrrs : 0
+  val_comb:
+  # for illegal csr
+    mode ==  'U' and mnemonic == "csrrs" and scause == ${CAUSE_ILLEGAL_INSTRUCTION} and stval == 0xfff72373 : 0    
+
+
+                  # These coverpoints will check that when load store address misaligned exception  
+                  # occurs does it correctly updates the valuse of the mcause and mtval 
+
+m_trap_test_load_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    "{lw , lh}" : 0
+  val_comb:
+    mode == 'M' and mnemonic == {"lw" , "lh"} and mcause == ${CAUSE_MISALIGNED_LOAD} and (mtval & 0x3) != 0: 0
+
+m_trap_test_store_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    "{sw , sh}" : 0
+  val_comb:
+    mode == 'M' and mnemonic == {"sw" , "sh"} and mcause == ${CAUSE_MISALIGNED_STORE} and (mtval & 0x3) != 0: 0
+
+s_trap_test_load_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{lw , lh}" : 0
+  val_comb:
+    mode == 'S' and mnemonic == {"lw" , "lh"} and mcause == ${CAUSE_MISALIGNED_LOAD} and (mtval & 0x3) != 0: 0
+
+s_trap_test_store_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{sw , sh}" : 0
+  val_comb:
+    mode == 'S' and mnemonic == {"sw" , "sh"} and mcause == ${CAUSE_MISALIGNED_STORE} and (mtval & 0x3) != 0: 0
+
+u_trap_test_load_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{lw , lh}" : 0
+  val_comb:
+    mode == 'U' and mnemonic == {"lw" , "lh"} and mcause == ${CAUSE_MISALIGNED_LOAD} and (mtval & 0x3) != 0: 0
+
+u_trap_test_store_m_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{sw , sh}" : 0
+  val_comb:
+    mode == 'S' and mnemonic == {"sw" , "sh"} and mcause == ${CAUSE_MISALIGNED_STORE} and (mtval & 0x3) != 0: 0
+
+
+                   # These coverpoints will check that when load store address misaligned exception 
+                   # occurs does it correctly updates the values of the scause and stval
+
+s_trap_test_load_s_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{lw , lh}" : 0
+  val_comb:
+    mode == 'S' and mnemonic == {"lw" , "lh"} and scause == ${CAUSE_MISALIGNED_LOAD} and (stval & 0x3) != 0: 0
+
+
+s_trap_test_store_s_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{sw , sh}" : 0
+  val_comb:
+    mode == 'S' and mnemonic == {"sw" , "sh"} and scause == ${CAUSE_MISALIGNED_STORE} and (stval & 0x3) != 0: 0
+
+
+u_trap_test_load_s_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{lw , lh}" : 0
+  val_comb:
+    mode == 'U' and mnemonic == {"lw" , "lh"} and scause == ${CAUSE_MISALIGNED_LOAD} and (stval & 0x3) != 0: 0
+
+
+u_trap_test_store_s_cause_tval:
+  config:
+    - check ISA:=regex(.*32.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True;
+  mnemonics:
+    "{sw , sh}" : 0
+  val_comb:
+    mode == 'U' and mnemonic == {"sw" , "sh"} and scause == ${CAUSE_MISALIGNED_STORE} and (stval & 0x3) != 0: 0
+
+
+

coverage/excp_msu/rv64i_excp_Mmode.cfg

@@ -0,0 +1,53 @@
+
+                                         # Address illegal instruction exceptions coverpoints #
+
+# This coverpoint will cover the illegal csr inappropriate csr and read only csr accesses, causing illegal instruction exceptions
+cp_M_excp_illegal:   
+  config:
+    - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    "{csrrw, csrrs, csrrc, ecall}": 0
+  val_comb:
+  # for illegal csr
+    mode ==  'M' and mnemonic == "csrrw" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0
+
+  # for inappropriate csr
+    mode ==  'M' and mnemonic == "csrrs" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # for read only csr
+    mode ==  'M' and mnemonic == "csrrc" and mcause == ${CAUSE_ILLEGAL_INSTRUCTION} : 0 
+
+  # When mstatus TVM bit is set, accessing satp and sfence.vma in M-Mode should not raise illegal instruction fault.
+    mode == "M" and (mstatus & ${MSTATUS_TVM} == ${MSTATUS_TVM}) and mnemonic == "csrrw" and satp != 0: 0
+
+
+
+                                # Address misaligned exceptions coverpoints #
+
+# coverpoint for the load address misaligned
+cp_M_load_addr_misaligned:
+  config:
+    - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    lw : 0
+  val_comb:
+    mode == 'M' and mnemonic == "lw" and mcause == ${CAUSE_MISALIGNED_LOAD} : 0
+
+# coverpoint for the store address misaligned
+cp_M_store_addr_misaligned:
+  config:
+    - check ISA:=regex(.*64.*); check ISA:=regex(.*I.*Zicsr.*); def rvtest_mtrap_routine=True;
+  mnemonics:
+    sw : 0
+  val_comb:
+    mode == 'M' and mnemonic == "sw" and mcause == ${CAUSE_MISALIGNED_STORE} : 0
+
+# this coverpoint is for ecall in machine mode  
+cp_M_ecall:
+  config: 
+    - check ISA:=regex(.*I.*); def rvtest_mtrap_routine=True 
+  mnemonics: 
+    ecall: 0
+  val_comb:
+  # for ecall
+    mode ==  'M' and mnemonic == "ecall" and mcause == ${CAUSE_MACHINE_ECALL} : 0