Added Tests and Coverage for Exception Handling(Illegal instruction, environment calls and misaligned address exceptions) and Trap State Restoration Exceptions #605
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…/s cause m/s tval csr after trap handling
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This has a misuse of ECALL in the test. IT should always set x2 to 0x1111_1111 to be handled by the trap handler properly. There also a misunderstanding of how unimplemented CSR are not handled in the spec (not guarnateed to trap), how misaligned occurs (may or may not trap), coments that don't seem to match the code.
The same procedue is used for all the test; it would make it more readable if you created a test macro for all the boilerplate to (greatly) reduce test size
| // get the address of the ecall instruction verify by checking both registers values | ||
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| // machine ecall | ||
| ecall |
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This must ensure that x2=0x1111_1111 because the trap handler will treat that as a parameter to the handler.
(if X2==0, this is GOTO_MMODE, =above value, it's the ECALL test, anything is is a test failure)
| LI (a4, CSR_MEDELEG) | ||
| csrw medeleg, a4 | ||
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| ecall // This exception will be handled in the machine mode |
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As above, T2 must ==0x1111_1111 else it will be treated as a test failure (note that if we ever change the existing ECALL test, this will have to change also)
| li t0, 0x3FC00000 // Hex representation of 1.5 in IEEE-754 single-precision | ||
| li t1, 0x40200000 // Hex representation of 2.5 in IEEE-754 single-precision | ||
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| // Move these values into floating-point registers |
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This test should also try a csrrd x2, FCSR (and FRM and FFLAGS to ensure that they trap also
| // mcause exception code will be "4" in U mode | ||
| */ | ||
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| LI (a4, 0x0008) |
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This is already tested in the misalign_lw_01.S test quite extensively. Also note that it very well might not trap, depending on misalign granularity
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| // This test will check that in machine mode, a store address misaligned exception is raised when we try | ||
| // to attempt to store data to a misaligned memory address. For this we will check the log file | ||
| // that either it is giving the expected exception at that point and value of the mcause is "6" in M mode |
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Same comment: this appears to be redundant with (much more extensive) tests that already exist.
| /* When we try to jump to the misaligned address then instead of instruction misaligned adddress it gives the illegal instruction exception */ | ||
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| // This test will check that in Supervisor mode, a load address misaligned exception will be raised |
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note that this may or may not trap, depending on the capabilities of the core
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| LA(x17,rvtest_data) | ||
| sw t1,0(x17) // will not give any exception | ||
| sw t2,3(x17) // will cause the exception |
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no guarantee that this will trap
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| // user ecall | ||
| ecall |
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usuall ecall issue: needs x2=0x1111_1111
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| LI (a4, 3) | ||
| csrrc t1,0xFFF,a4 // accessing non existing CSR will generate the illegal instruction exception |
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no guaratnee this will cause an excpetion
| nop | ||
| nop | ||
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| ecall // This exception will be handled in the Supervisor mode |
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