Sync master into dev #3566
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Sync master into dev #3566
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Cherry-picked chipsalliance/chisel@7372c9e Should use BarrelShifter from chisel3.std, but it is not published, see chipsalliance/chisel#2997
scala.reflect.internal.Types: constructor RecordMap in class RecordMap cannot be accessed in package util from package util in package rocketchip
It is not rs2, it is imm Related to #3255
This removes a redundant port As rnum is encoded in rs2 as imm now, we can get it just from rs2
This was introduced by "(185cac8) Add hypervisor extension (#2841)" This is a dead code, as no circuit is producing and consuming this bit. This was discovered when migrating Core.scala to chisel3, where strict checking was applied for IO and firrtl found this is not connected. In the context of hypervisor extension, V bit, or _virtualization mode_, indicates whether the hart is currently executing in a guest. For TLBReq, the V bit is needed as it affects the PTW thus TLB behavior on whether to do _Two-Stage Address Translation_. However, the bit is not needed for TLBException. The exceptions (pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point to add V bit for gf (guest page fault). The io.resp.gf added below in the original patch also does not connect io.resp.gf.v. If this V bit should be added for this specific exception, it should be connected. I assume this was added accidentally, as the original "extends CoreBundle()(p)" modification seems irrelevant.
(cherry picked from commit 34d7309)
(cherry picked from commit a2682ca)
(cherry picked from commit 0e4af6d)
Relax dependencies on HasPeripheryDebug (backport #3279)
Nix 2.14 released with incompatibilities with cachix/install-nix-action. This PR pins nix to 2.13.3 to avoid CI fails See: cachix/install-nix-action#161 (cherry picked from commit 84533ae)
(cherry picked from commit 1ff0db3)
(cherry picked from commit e645d94)
(cherry picked from commit d6a982b)
(cherry picked from commit b2fd991)
L1TLB: VS-mode SFENCE misses tera/giga-page entries fragmented superpages (backport #3297)
Reset recv_beat (cherry picked from commit f19a90a)
RoCC accesses D$, not I$ (cherry picked from commit 61ea81c)
riscv-tests.suite[] wont compile (cherry picked from commit d86c011)
Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled (backport #3314)
Change CharCountRoCC Example to use dcacheParams (backport #3304)
Remove SCIE interface (backport #3499)
Remove vsim/emulator flows, add simple make verilog flow (backport #3494)
(cherry picked from commit b47fdf9) Co-authored-by: Jerry Zhao <[email protected]>
(cherry picked from commit b2b78fd)
(cherry picked from commit 4dc6305)
Add DelayQueue (backport #3520)
(cherry picked from commit df66c19)
(cherry picked from commit 74dd9b1)
(cherry picked from commit 5bef59a) # Conflicts: # src/main/scala/tile/Core.scala
(cherry picked from commit 218ae0a)
Remove Scalar Crypto and BitManip (copy #3532)
…d by the manuals. * Fix the mapping when we access scontext or hcontext to ensure we don't switch targets. * Add comment to indicate why we are mapping the S to VS and VS to S.
SContext is remaps to HContext when in VSMode
Support vector-units w/o L1D$ access (copy #3537)
fixing tech report broken link
Change a_sublane to also check the mask to see if the transaction a partial write. Improves throughput in cases when the full bus is being utilized
Update ECC SRAM to improve throughput on full write
…t-link Fix outdated technical report link.
Update README.md
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Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
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