Merge pull request #3566 from chipsalliance/sync

Sync master into dev

README.md

@@ -2,7 +2,7 @@ Rocket Chip Generator :rocket: ![Build Status](https://github.com/chipsalliance/
 =====================
 
 This repository contains the Rocket chip generator necessary to instantiate
-the RISC-V Rocket Core. For more information on Rocket Chip, please consult our [technical report](http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html).
+the RISC-V Rocket Core. For more information on Rocket Chip, please consult our [technical report](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html).
 
 ## RocketChip Dev Meeting
 
@@ -233,4 +233,4 @@ A list of contributors can be found [here](https://github.com/chipsalliance/rock
 
 If used for research, please cite Rocket Chip by the technical report:
 
-Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, _[The Rocket Chip Generator](http://www.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html)_, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016
+Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, _[The Rocket Chip Generator](https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html)_, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016

src/main/scala/rocket/CSR.scala

@@ -847,10 +847,17 @@ class CSRFile(
     val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap
 
     for ((k, v) <- unvirtualized_mapping) yield k -> {
-      val alt = CSR.mode(k) match {
-        case PRV.S => unvirtualized_mapping.lift(k + (1 << CSR.modeLSB))
-        case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
-        case _ => None
+      val alt: Option[Bool] = CSR.mode(k) match {
+        // hcontext was assigned an unfortunate address; it lives where a
+        // hypothetical vscontext will live.  Exclude them from the S/VS remapping.
+        // (on separate lines so scala-lint doesnt do something stupid)
+        case _ if k == CSRs.scontext => None
+        case _ if k == CSRs.hcontext => None
+        // When V=1, if a corresponding VS CSR exists, access it instead...
+        case PRV.H                   => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
+        // ...and don't access the original S-mode version.
+        case PRV.S                   => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)
+        case _                       => None
       }
       alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)
     }

src/main/scala/tilelink/SRAM.scala

@@ -229,8 +229,9 @@ class TLRAM(
     val r_ready = !d_wb && !r_replay && (!d_full || d_ready) && (!r_respond || (!d_win && in.d.ready))
     in.a.ready := !(d_full && d_wb) && (!r_full || r_ready) && (!r_full || !(r_atomic || r_sublane))
 
+    // ignore sublane if mask is all set
     val a_sublane = if (eccBytes == 1) false.B else
-      in.a.bits.opcode === TLMessages.PutPartialData ||
+      ((in.a.bits.opcode === TLMessages.PutPartialData) && (~in.a.bits.mask.andR)) ||
       in.a.bits.size < log2Ceil(eccBytes).U
     val a_atomic = if (!atomics) false.B else
       in.a.bits.opcode === TLMessages.ArithmeticData ||