FIRRTL v1.4.1

Highlights

• Speed up writing CustomFileEmission with buffering (#1906)
• Refactor emitter, includes split big Emitter to submodules (#1879)
• SMT: ensure that all signals have a unique name (#1943)
• Automatically publish SNAPSHOTs on pushes to master (#1955) (#2002)(#2004)
• Add SortModules Transform (#1905)

API Changes

• (addition) Make MultiTargetAnnotation.targets a def, more flexibility for annotation writers (#1969)

Bug fixes

• Fix problem with nested subaccess (#1984)
• Fix negative literals > 32 bits (#1915) (#1918)
• VerilogMemDelays: fix lowering of direct mem-to-mem connections (#1908)
• Fix SMT Memory Bug (#1942)(#1951)
• Fix RemoveWires handling of invalidated non-UInt wires (#1949)
• Fix Type Error fuzzer Example code (#1960)

Miscellany

• Make LazyLogging log to console by default. (#1961)
• Improve Travis Chisel tests (#1903)
• Add test for chaining RW-port rdata as wdata of another mem
• Improve Travis Chisel tests (#1903)
• License reference in maven publishing info now points to apache 2.0 (#1907)
• Add SPDX comment to all source Scala and Verilog files (#212) (#213)
• Add MiMa binary compatibility checking (#1922)
• Remove caching from RenameMap (#1938) (#1939)
• -full64 is required to detect VCS. (#1930) (#1941)
• Add weak and strong to Utils.v_keywords (#1983)

FIRRTL v1.4.0

Highlights

• Inline Boolean Expressions (#1817)

Boolean expressions that share a common source locator line will now be inlined in the emitted Verilog.
This can be disabled with --pretty:no-expr-inlining (#1869)

• Annotations no longer prevent Deduplication (#1539)

Deduplication will turn annotations into instance targets, disambiguating annotations that differ between different instances of the same module. This is the first time that instance target behavior is used extensively and may cause problems in custom transforms.

• Custom Serialization of Annotations (#1277)

This adds an Annotation mix-in, CustomFileEmission, that allows an annotation to declare how it should be serialized to a file.

• Avoid repeated inlining in FlattenRegUpdate (#1727)

FIRRTL no longer creates and emits unreachable paths in if-else logic.

• Propagate source locators to register update always blocks (#1743)

Source locators are now present in emitted always blocks. Source locators are also now more accurate for ternary operators and if-else blocks that derive from when blocks.

• Relicensed to Apache 2.0 (#1901)
• Add support for Scala 2.13 (#1796) - Note that Chisel does not yet support Scala 2.13

Deprecations

• Deprecate support for Scala 2.11 (#1842)
• Deprecate PreservesAll trait, Remove Usages (#1700)
• Deprecate CompilerAnnotation (#1870)
• Deprecate Uniquify (it's now part of LowerTypes) (#1856)
• Deprecate more firrtl.Compiler methods (#1791)
• Deprecate InstanceGraph in favor of InstanceKeyGraph (#1800)
• Deprecating BackendCompilationUtilities trait for object (#1575)

API Modifications

• when-otherwise scopes are now checked (#1528)

This is not really an API modification but code that formerly was accepted will now be rejected.

• Make StageOption Unserializable (#1891)

The StageOption annotations will no longer be serialized in output annotation files. In particular, this includes TargetDirAnnotation.

• Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)

Const Prop and DCE will preserve deduplication even if instances of the same module have differing "dont touch" annotations.

• RenameMap: remove implicit rename chaining (#1591)
• Remove Left Over References to Gender in Code (#1752)
• Remove LegacyAnnotation and [most] MoultingYaml, Remove all uses of ConvertLegacyAnnotations (#1833)
• Error on ExtModules w/ same defname, different ports (#1734)

Fixes

• Async reset tieoff bug (#1854)
• Legalize mem clocks (#1883)
• Fix Uniquify bug and improve ReplaceSeqMems transforms (#1855)
• Emit parentheses in Verilog for nested unary ops (#1865)
• FlattenSpec: flattening a module with no instances is now a no-op (#1868)
• Add some missing transform invalidations (#1541)
• Make WrappedTransform work with --class-log-level (#1640)
• Set prerequisite of -X high to MinimalHighForm (restores FIRRTL 1.2 behavior) (#1704)
• Mask bits when propagating bitwise ops (#1745)
• Fix reduction op bug ConstantPropagation (#1746)
• Make TopWiringTransform run before LowerTypes (#1750)
• Make InferWidths thread safe (#1775)
• Update negative literal emission (#1782)
• Fix sign extension issue in Emitter add sign-extend const-prop test (#1785)
• WiringTransform: fix non-determinism (#1799)
• Fixed typo in fixed-point type parameter examples (#1816)
• Make Utils.expandRef actually return intermediate expressions per API docs (#1624)
• Fix RemoveIntervals invalidations (#1689)
• Add support for ValidIf to ProtoBuf [de]serialization (#1707)
• Don't Dedup modules if it would change semantics (#1713)
• Fix parsing of info on multi-line registers (#1735)
• RemoveWires: improve dependencies and declare ResolveKinds as an invalidation (#1797)

Feature

• Group _RAND_# declarations and guard with ifdef in emitted Verilog (#1548)
• Better error messages for unserializable annotations (#1885)
• Cleanup Named Targets (#1311)
• Apply Scalafmt Rewriting (#1852)
• Support Memory Initialization for Simulation and FPGA Flows (#1645)
• Canonicalize init of regs with zero as reset in RemoveReset (#1627)
• Refactor ManipulateNames to use Target, add --change-name-case <lower|upper> option (#1638)
• Move Verilog initialization code to end of module (#1613)
• Add firrtl.stage.Forms.AssertsRemoved for new formal transforms (#1754)
• Add macros around Verilog initial blocks (#1550)
• Constant Prop Reduction Operations of Literals (#1558)
• Add LegalizeAndReductionsTransform (#1556) Workaround for https://github.com/verilator/verilator#2300
• Add basic transform benchmarking infrastructure and speed up Resolve Kinds (#1475)
• Do not throw NonFatal exceptions during annotation logging (#1639)
• Add support for Verilog attributes (#1643)
• Merge WIR and IR (#1649)
• Add experimental SMT Backend (#1826)
• Add mapString method to ir.Port (#1655)
• Limit recursion (and reduce total work) in CheckWidths (#1646)
• Speed up ExpandWhens for very large designs (#1666)
• Build ArrayBuffers in Block.mapStmt (#1669)
• Speed up CheckHighForm (#1582)
• Have AppendInfo use MultiInfo, rather than appending with : (#1580)
• Don't try deduplicating the main module of a circuit (#1594)
• consolidated wire+assign to just wire, with expression inlined (#1600)
• Speed up InferTypes and CInferTypes (#1601)
• Speed up Deduplication, Remove accidental hashing of all Modules in Dedup (#1602)
• Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)
• Add scaladoc for LogicNode and tighten LowForm-only constraint in CheckCombLoops (#1635)
• Compiler: demote compile time logging to info-level instead of error (#1685)
• Fix determinism in dependency manager (#1686)
• Store FileInfo string in escaped format (#1690)
• Add faster IR serializer (#1694)
• Emit verification node message as Verilog comment (#1712)
• Batch renames in LowerTypes (#1718)
• Enable flow from assert to print + stop (#1725)
• Use structural sha256 hash in Deduplication instead of agnostify and serialize (#1731)
• Faster dedup instance graph (#1732)
• Add Expression Fuzzer for testing FIRRTL itself (#1741)
• Add Firrtl plugin info for intellij platform (#1547)
• Strip dependencies from BlackBoxSourceHelper (#1840)

FIRRTL specification changes

• Explicitly disallow shadowing of component names (#1749)
• Clarify spec definition of indentation and when/else indentation (#1565)
• Fix typos (#1626) (#1564)

Miscellany

• Add parse_firrtl_transform_log utility script (#1543)
• Add find_heap_bound.py script for finding minimum heap size (#1648)
• Bump to Scala 2.12.12 (#1847)
• Update antlr4-runtime to 4.7.2 (#1720)
• Update json4s-native to 3.6.9 (#1692)
• Update moultingyaml to 0.4.2 (#1480)
• Update protoc-jar to 3.11.4 (#1434)
• Update sbt to 1.3.10 (#1529)
• Update sbt-buildinfo to 0.10.0 (#1529)
• Update sbt-scalafix to 0.9.15 (#1529)

v1.4.0-RC1

API Modification

(#1277) File Serialization of Annotations
This adds an Annotation mix-in, HowToSerialize, that allows an
annotation to declare how it should be serialized to a file.
A lot of work here. Please check PR

(#1591) RenameMap: remove implicit rename chaining

(#1700) Deprecate PreservesAll Trait, Remove Usages

(#1752) Remove Left Over References to Gender in Code

(#1809) ir: use Serializer.serialize where possible, serialize MultiInfo correctly

(#1833) Remove LegacyAnnotation and [most] MoultingYaml, Remove all uses of ConvertLegacyAnnotations

Features

(#1311) Cleanup Named Targets
Adds a new transform, CleanupNamedTargets, that will convert
ReferenceTargets to InstanceTargets if any ReferenceTargets are found
to be actually pointing at instances.

(#1852) Apply Scalafmt Rewriting

(#1541) Add Some Missing Invalidations
This adds missing invalidations to four transforms:

• ExpandConnects
• RemoveAccesses
• SplitExpressions
• VerilogMemDelays

(#853) Equivalence tests

• firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct
• add RemoveValidIf pass to MinimumLowFirrtlOptimization

(#1645) Support Memory Initialization for Simulation and FPGA Flows
Support Memory Initialization for Simulation and FPGA Flows

(#1627) Canonicalize init of regs with zero as reset in RemoveReset
Canonicalize init of regs with zero as reset in RemoveReset

(#1638) Refactor ManipulateNames to use Target, Add --change-name-case <lower|upper> option
Refactor RemoveKeywordCollisions->ManipulateNames
This adds three new transforms:

• (abstract) LetterCaseTransform parent of case manipulation
• LowerCaseNames to lower case all names
• UpperCaseNames to upper case all names

(#1640) Make WrappedTransform work with --class-log-level

(#1654) Fix performance regression in DedupModules

(#1704) Set prerequisite of -X high to MinimalHighForm

(#1726) Fix botched type match in ManipulateNames

(#1734) Error on ExtModules w/ same defname, diff. ports
Adds a high form check to ensure that external modules that have the
same defname also have exactly the same ports.

(#1745) mask bits when propagating bitwise ops
ConstProp: test bitwise op of signed literals, use bit mask for FoldOr/FoldXor handle and also add UIntLiteral.masked helper

(#1746) fix reduction op bug ConstantPropagation

(#1750) Make TopWiringTransform run before LowerTypes
This fixes a bug where top-wired wire bundles with flips could result
in the top-wired, flattened bundle having every field with an "output"
direction if the TopWiringTransform is moved around in the transform
order (see FIRRTL issue #1744).

(#1754) Integrate new transforms with firrtl.stage.Forms
Integrate new transforms with firrtl.stage.Forms
Two transforms associated with converting and removing the new
verification statements are moved into a new set of transforms,
AssertsRemoved:

• firrtl.transforms.formal.ConvertAsserts
• firrtl.transforms.formal.RemoveVerificationStatements

(#1539) Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (without AST targets)
Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths
[wip] Add MorphismSpec

(#1775) Make InferWidths thread safe

(#1782) Update negative literal emission

(#1785) Fix sign extension issue in Emitter add sign-extend const-prop test

(#1799) WiringTransform: fix non-determinism

(#1816) Fixed typo in fixed-point type parameter examples

(#1829) ExpandWhens: VerificationStatements should be part of the simlist

(#1845) Rollback scalatest to avoid printing bug

(#1528) Create new scopes for child statements of Conditionally
Fix out-of-scope reference in handwritten CHIRRTL mem test
Update RightShiftTests.fir to avoid buggy Counter pattern, see: #1505

(#1550) before/after initial block macros, adding init macros

(#1548) Emitter: guard RAND* declarations with ifdef
Emitter: add declare functions ifdef guard
Emitter: add ifdef initials
Emitter: add comments, cleanup
Emitter: changes from code review

• make new methods private
• use .withDefault
• remove empty initial block

(#1558) Constant Prop Reduction Operations of Literals

(#1556) Add LegalizeAndReductionsTransform
Add LegalizeAndReductionsTransform. Workaround for https://github.com/verilator/verilator #2300

(#1613) moving initializations to end of module

(#1622) Add basic transform benchmarking infrastructure and speed up Resolve Kinds (bp #1475)

(#1624) Make Utils.expandRef actually return intermediate expressions per API docs

(#1639) Improve anno logging
Do not throw NonFatal exceptions in annotation logging
DRY out transform running and annotation remapping
Do not throw NonFatal exceptions in annotation logging

(#1643) recore of Attributes
Add attributes, ifdefs to emitter.
Make ifdef API a little cleaner.

(#1649) WIR/IR merge part 2: more IR factories, update tutorial
Update tutorial to reflect IR/WIR forms being merged

(#1648) Find Heap Bound, Add find_heap_bound.py script for finding minimum heap size

(#1826) SMT Backend

(#1655) Add mapString method to ir.Port
(#1663) Limit recursion (and reduce total work) in CheckWidths (bp #1646)
(#1666) Speed up ExpandWhens for very large designs
(#1669) Build ArrayBuffers in Block.mapStmt
(#1672) Update Mergify to refer to travis-ci.com

(#1582) Speed up CheckHighForm
(#1580) Have AppendInfo use MultiInfo, rather than appending with :
(#1594) Don't try deduping the main module of a circuit
(#1600) consolidated wire+assign to just wire, with expression inlined
(#1601) Speed up InferTypes and CInferTypes
(#1602) Speed up Deduplication, Remove accidental hashing of all Modules in Dedup
(#1603) Implement CircuitGraph and IRLookup to firrtl.analyses
(#1635) Add scaladoc for LogicNode and tighten LowForm-only constraint
(#1685) Compiler: demote compile time to info instead of error
(#1686) delete usages of toSet for determinism
(#1689) RemoveIntervals: fixup kinds of refs to replaced nodes
(#1690) ir: store FileInfo string in escaped format
(#1694) ir: add faster serializer
(#1709) Add support for ValidIf to ProtoBuf [de]serialization (bp #1707)
(#1712) verification: emit mesage as Verilog comment
(#1713) Don't Dedup modules if it would change semantics
(#1717) verification: clarify the meaning of verification statement in warnig message
(#1718) Batch renames in LowerTypes
(#1725) Enable flow from assert to print + stop
(#1727) Avoid repeated inlining in FlattenRegUpdate
(#1731) dedup: use structural sha256 hash instead of agnostify and serialize
(#1732) Faster dedup instance graph
(#1735) Fix parsing of info on multi-line registers
(#1741) Add Expression Fuzzer
(#1743) Propagate source locators to register update always blocks
(#1749) [spec] Explicitly disallow shadowing of component names
(#1796) Scala 2.13 support. WIP
(#1797) RemoveWires: improve dependencies and declare ResolveKinds as an invalidation
(#1800) Deprecate InstanceGraph
(#1813) CircuitGraph: remove fields from public API
(#1547) add Firrtl plugin info for intellij platform

Miscellany

(#1793) Add Treadle publishLocal to CI for Chisel3 Tests
(#1791) Add deprecations for more firrtl.Compiler methods
(#1543) Add parse_firrtl_transform_log utility script
(#1847) Bump Scala 2.12.12
(#1762) Change ProtoBuf generated directory
(#1565) Clarify spec definition of indentation and when/else indentation
(#1772) Cross-build unidoc in CI
(#1842) Deprecate support for Scala 2.11
(#1795) Fix incorrect error message
(#1542) Fix remaining 'removed in 1.3' deprecations
(#1626) Fix typo in spec description of 'tail'
(#1564) Fix typos in the specification.
(#1840) Strip dependencies from BlackBoxSourceHelper
(#1573) Update Travis cache for SBT 1.3
(#1720) Update antlr4-runtime to 4.7.2
(#1692) Update json4s-native to 3.6.9
(#1480) Update moultingyaml to 0.4.2
(#1434) Update protoc-jar to 3.11.4
(#1529) Update sbt to 1.3.10
(#1834) Update sbt-buildinfo to 0.10.0
(#1536) Update sbt-scalafix to 0.9.15
(#1837) Update scalacheck-1-14, ... to 3.1.3.0
(#1584) Update scalatest to 3.1.2
(#1675) Use Travis Workspaces
(#1761) add .bloop and .metals to .gitignore
(#1575) deprecating BackendCompilationUtilities trait for object
(#1831) scalatest: upgrade to 3.2.1
(#1839) tests: Decrease Dependency on Deprecated APIs

v1.3.2

(#1581) Make benchmark_cold_compile.py work even if it can't fetch
(#1612) Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms
(#1622) Add basic transform benchmarking infrastructure and speed up Resolve Kinds
(#1630) Canonicalize init of regs with zero as reset in RemoveReset
(#1632) Fix typo in spec description of 'tail'
(#1633) Don't try deduping the main module of a circuit
(#1637) Add scaladoc for LogicNode and tighten LowForm-only constraint
(#1642) Improve annotation logging
(#1658) Fix/update a few Scaladoc links
(#1660) Add mapString method to ir.Port
(#1661) Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms
(#1663) Limit recursion (and reduce total work) in CheckWidths
(#1667) [1.3.x] Bump Mima check to 1.3.1
(#1674) Speed up ExpandWhens for very large designs
(#1677) Use Travis Workspaces
(#1682) Find Heap Bound, Refactor benchmark_code_compile.py to have job running utility
(#1684) Build ArrayBuffers in Block.mapStmt
(#1688) delete usages of toSet for determinism
(#1705) Set prerequisite of -X high to MinimalHighForm
(#1709) Add support for ValidIf to ProtoBuf [de]serialization
(#1715) Don't Dedup modules if it would change semantics

v1.2.7

(#1611) consolidated wire+assign to just wire, with expression inlined
(#1616) Speed up InferTypes and CInferTypes
(#1623) Backport ResolveKinds improvements
(#1629) Canonicalize init of regs with zero as reset in RemoveReset
(#1631) Fix typo in spec description of 'tail'
(#1636) Add scaladoc for LogicNode and tighten LowForm-only constraint
(#1657) Fix/update a few Scaladoc links
(#1662) Limit recursion (and reduce total work) in CheckWidths
(#1668) Bump Mima check to 1.2.6
(#1673) Speed up ExpandWhens for very large designs
(#1676) Use Travis Workspaces
(#1708) Add support for ValidIf to ProtoBuf [de]serialization
(#1714) Don't Dedup modules if it would change semanticS

v1.3.1

Fix

(#1571) Clarify spec definition of indentation and when/else indentation (bp #1565)
(#1593) Fix typos in the specification. (bp #1564)

Feature

(#1551) [1.3.x] Add binary compatibility checking to CI
(#1553) Emitter: guard RAND* declarations with ifdef (bp #1548)
(#1555) Add Some Missing Invalidations (bp #1541)
(#1559) Add LegalizeAndReductionsTransform (bp #1556)
(#1566) Update scalatest to 3.1.1 (bp #1405)
(#1567) Update protoc-jar to 3.11.4 (bp #1434)
(#1568) Update moultingyaml to 0.4.2 (bp #1480)
(#1569) Update sbt to 1.3.10 (bp #1529)
(#1570) Update sbt-scalafix to 0.9.15 (bp #1536)
(#1574) Update Travis cache for SBT 1.3 (bp #1573)
(#1578) backporting initialization macro PRs
(#1583) Speed up CheckHighForm (bp #1582)
(#1588) Constant Prop Reduction Operations of Literals (bp #1558)
(#1590) Have AppendInfo use MultiInfo, rather than appending with : (bp #1580)
(#1605) add Firrtl plugin info for intellij platform (#1547)
(#1608) Update scalatest to 3.1.2 (bp #1584)
(#1609) consolidated wire+assign to just wire, with expression inlined (bp #1568)
(#1614) Scala steward 1476 (bp #1606)
(#1615) Scala steward 1560 (bp #1607)
(#1617) Speed up InferTypes and CInferTypes (bp #1601)
(#1620) Speed up Deduplication (bp #1602)

v1.2.6

Fix

(#1518) Fix mixed -E and -e emission (bp #1512)

Feature

(#1596) Add LegalizeAndReductionsTransform, workaround for Verilator bug (bp #1556)
(#1604) add Firrtl plugin info for intellij platform (#1547)
(#1619) Speed up Deduplication (bp #1602)

v1.3.0

API Modification

(#1123) Dependency API 2 (take 3) Migrate to DependencyAPI
(#1258) Remove scala-logging fully in favor of our own logger
(#1265) Remove Stage-global --no-dedup Option
(#1357) Omnibus Dependency API Updates
(#1387) Include Dead Modules in InstanceGraph.staticInstanceCount
(#1412) [RFC] Factor-out common test classes; package them
(#1413) Remove DiGraph.seededLinearize
(#1440) Remove dead passes.DeadCodeElimination code
(#1447) Revert Compiler.execute to public (was protected)
(#1461) Change annotation logging
(#1534) Trait-base Dependency API Migration

Fix

(#1217) Add explicit EOF to top-level parser rule - Fixes #1154
(#1228) getSimpleName considered harmful
(#1238) Error on nested memory datatypes
(#1241) bug fix for chipsalliance/chisel#1240
(#1266) Remove incorrect --firrtl-source option
(#1278) {Firrtl, Circuit}Option should be Unserializable
(#1282) Fix incorrect ScalaDoc link
(#1288) Make EmittedAnnotation Unserializable
(#1307) Change LoggerState.globalLevel to Warn
(#1310) Filter ResolvePaths in EliminateTargetPaths
(#1349) Fix conversion of Reference-containing expressions to ReferenceTargets
(#1362) Add note to spec about reductions on zero-width wires - Fixes #1344
(#1366) Better register const prop through speculative de-optimization - Fixes #1240
(#1370) Rename Modules Duplicated by EliminateTargetPaths
(#1374) Fixing lint error: x + -1
(#1388) Allow self renames
(#1392) Short Circuit resolvePaths if no Targets
(#1394) EliminateTargetPaths and Unreachable Modules
(#1396) Remove last connect semantics from reset inference
(#1397) Add test: driving multiple downstream reset types with cast
(#1418) Fix error message for NegWidthException
(#1422) Revert inline nots
(#1437) Check for name collisions of Modules - Fixes #1436, #1096, #1214
(#1450) Fix dynamic SubAccess of zero-length vectors - Fixes #230
(#1454) Make InlineInstances invalidate ResolveKinds - Fixes #1453
(#1474) Fix InlineCasts
(#1478) Support all the bases (octal/bin) outlined in the spec (bp #1477) - Fixes #1464
(#1504) EliminateTargetPaths: don't duplicate modules with only one instance
(#1512) Fix mixed -E and -e emission
(#1519) Always run PadWidths when generating Verilog
(#1523) Allow casts in AsyncReset literal value check
(#1525) Prevent infinite recursion in CheckResets - Fixes #1516
(#1542) Fix remaining 'removed in 1.3' deprecations - Fixes #1467

Feature

(#782) Support infoMode for Strings
(#1050) (Finally?) Add Support for Bitstream Preset-registers
(#1190) Logger comment tweaks
(#1191) Add check for multiple sources for same wiring pin
(#1206) Add separate Issue and PR templates
(#1211) Supply a trait to allow user annotations to provide JsonProtocol type hints
(#1216) Change findInstancesInHierarchy to return implicit top instance
(#1218) Ignore extmodule instances in Flatten - Closes #1162
(#1219) Guard initial blocks in emitted Verilog with ifndef SYNTHESIS
(#1222) Add spec for Analog type and attach statement - Closes #1194
(#1224) Move CheckResets after CheckCombLoops
(#1231) Use Mergify to automate backporting to 1.2.x
(#1243) Make updated type info available in VerilogMemDelays - Closes #1242
(#1245) [Mergify] Automatically merge backport PRs when ready
(#1259) Cleanup testing console
(#1264) Cleanup verilog emitter casts
(#1270) Verilog emitter transform InlineNots
(#1271) Make the member 'logger' added by the trait LazyLogging protected.
(#1275) Support object transforms
(#1284) Improve Scaladoc
(#1286) Repl seq mem renaming
(#1291) Infer resets last connect semantics
(#1296) Verilog emitter transform InlineBitExtractions
(#1297) Fix .run_formal_checks.sh skipping logic
(#1302) Dedup PassTests, add NoCircuitDedupAnnotations
(#1305) Change default LogLevel to Warn
(#1315) clean up warnings: trim unused imports
(#1317) Refactoring checkCatArgumentLegality
(#1321) add IsModule, IsMember, CompleteTarget serializers
(#1323) Dedup: check if moduleOpt exists before getting
(#1324) Fix copy-paste error in DiGraph.linearize documentation
(#1326) Update sbt-scalafix to 0.9.11
(#1327) Update sbt-assembly to 0.14.10
(#1328) Update sbt-buildinfo to 0.9.0
(#1329) Update sbt-unidoc to 0.4.2
(#1330) Update protoc-jar to 3.11.1
(#1331) Update sbt-antlr4 to 0.8.2
(#1332) Update junit to 4.13
(#1333) Update commons-text to 1.8
(#1335) Update sbt-scoverage to 1.6.1
(#1336) Update scalacheck to 1.14.3
(#1345) Update sbt-unidoc to 0.4.3
(#1354) Update sbt to 1.3.8
(#1355) Add constant prop to async regs
(#1359) Emit 'else' case for trivial-valued async reset regs to avoid latches
(#1361) Constant prop binary PrimOps with matching arguments
(#1367) Support MemConfs with very deep memories
(#1368) Mill Support
(#1375) Add reviewer checklist / update contributor checklist
(#1378) [spec] Change sub(UInt, UInt) output type to UInt
(#1381) Removed unused imports in src/test/
(#1382) Update ScalaTest deprecations.
(#1383) Update scalatest 3.1.0
(#1391) Add InstaceGraph (Un)?Reachable Helpers
(#1399) Revert "Repl seq mem renaming (#1286)"
(#1401) Add more docs / tests for DiGraph reachableFrom method
(#1407) sbt compatible publish for mill
(#1408) mill: add testOnly
(#1409) [spec] clarify that div-by-zero is undefined
(#1414) Update single-line when/else example in spec to match implementation - Closes #890
(#1416) Remove RenameMap logging from EliminateTargetPaths
(#1420) Support Java API doc Scaladoc/Unidoc References
(#1421) Check sign of primop constants where appropriate
(#1423) Clone Verilator from GitHub, fix tag name
(#1424) Revert inline nots only 1.2.x (bp #1422)
(#1429) Make mergify open backport PRs & signal on failed cherry-picks
(#1430) Add firrtl-json serializers
(#1433) Provide an annotation mix-in that marks RTs as dontTouch
(#1439) [mergify] Update match string for labeling backported PRs
(#1448) Avoid generating out-of-bounds indices in ReplaceAccesses (bp #1446)
(#1449) Remove toNamed (and friends) deprecation.
(#1451) Update Mid FIRRTL spec to reflect removal of subaccesses
(#1456) [spec] Add Fixed to spec - Fixes #1195
(#1458) Add method to CheckCompLoops which returns its full netlist
(#1463) Explicitly initialize firrtl.stage.Forms to prevent multi-thread collisions
(#1465) Refactor build.sbt into more normal style
(#1470) Eliminate warnings on sbt doc and sbt unidoc
(#1471) Nuclear Option (-Xfatal-warnings) for Scaladoc Build
(#1473) Bump to Scala 2.12.11
(#1482) Add 'did you update spec' box to PR template
(#1493) Disable unidoc -Xfatal-warning for Scala 2.11
(#1495) Add Release Notes section and check-box for checklist.
(#1496) Split Passes.scala into separate files
(#1497) Remove deprecated gender
(#1502) Add ground type serializer
(#1510) Verilog Emitter: move asyncInitials inside initial block RANDOMIZE ifdef
(#1517) Split Checks & Resolves into separate files (bp #1508)
(#1520) Add new test jar to .gitignore
(#1522) Always run PadWidths when generating Verilog (bp #1519)
(#1530) Check width for asClock / asAsyncReset
(#1537) Change dependents to optionalPrerequisiteOf

v1.3.0-RC3

API Modification

(#1534) Trait-base Dependency API Migration

Fix

(#1504) EliminateTargetPaths: don't duplicate modules with only one instance
(#1512) Fix mixed -E and -e emission
(#1519) Always run PadWidths when generating Verilog
(#1523) Allow casts in AsyncReset literal value check
(#1525) Prevent infinite recursion in CheckResets - Fixes #1516

Feature

(#782) Support infoMode for Strings
(#1456) [spec] Add Fixed to spec - Fixes #1195
(#1496) Split Passes.scala into separate files
(#1502) Add ground type serializer
(#1510) Verilog Emitter: move asyncInitials inside initial block RANDOMIZE ifdef
(#1517) Split Checks & Resolves into separate files (bp #1508)
(#1520) Add new test jar to .gitignore
(#1530) Check width for asClock / asAsyncReset
#1537) Change dependents to optionalPrerequisiteOf

v1.2.5

Fix

(#1438) Fix copy-paste error in DiGraph.linearize documentation (bp #1324)
(#1444) Don't const-prop a register's self-init (bp #1441) Fixes #1214
(#1448) Avoid generating out-of-bounds indices in ReplaceAccesses (bp #1446)
(#1455) Make InlineInstances invalidate ResolveKinds (bp #1454) Fixes #1453
(#1457) Check for name collisions of Modules (bp #1437) Fixes #1436, #1096
(#1478) Support all the bases (octal/bin) outlined in the spec (bp #1477) Fixes #1464
(#1481) Fix InlineCasts (bp #1474)
(#1501) Fix dynamic SubAccess of zero-length vectors (bp #1450) Fixes #230
(#1514) [spec] Add Fixed to spec (bp #1456) Fixes #1195
(#1522) Always run PadWidths when generating Verilog (bp #1519)
(#1527) Prevent infinite recursion in CheckResets (bp #1525) Fixes #1516

Feature

(#1432) Add firrtl-json serializers (bp #1430)
(#1443) Update MiMa check to include all 1.2.x releases
(#1452) Update Mid FIRRTL spec to reflect removal of subaccesses (bp #1451)
(#1459) Add method to CheckCompLoops which returns its full netlist (bp #1458)
(#1468) Remove toNamed (and friends) deprecation. (bp #1449)
(#1469) Support Java API doc Scaladoc/Unidoc References (bp #1420)
(#1483) Add InstaceGraph (Un)?Reachable Helpers (bp #1391)
(#1485) Allow self renames (bp #1388)
(#1486) EliminateTargetPaths and Unreachable Modules (bp #1394)
(#1491) Remove RenameMap logging from EliminateTargetPaths (bp #1416)
(#1499) Add Release Notes section and check-box for checklist. (bp #1495)
(#1506) Add ground type serializer (bp #1502)
(#1507) Split Passes.scala into separate files (bp #1496)
(#1509) EliminateTargetPaths: don't duplicate modules with only one instance (bp #1504)
(#1515) Verilog Emitter: move asyncInitials inside initial block RANDOMIZE ifdef (bp #1510)
(#1517) Split Checks & Resolves into separate files (bp #1508)
(#1524) Allow casts in AsyncReset literal value check (bp #1523)