This repository has been archived by the owner on Aug 20, 2024. It is now read-only.
v1.2.7
(#1611) consolidated wire+assign to just wire, with expression inlined
(#1616) Speed up InferTypes and CInferTypes
(#1623) Backport ResolveKinds improvements
(#1629) Canonicalize init of regs with zero as reset in RemoveReset
(#1631) Fix typo in spec description of 'tail'
(#1636) Add scaladoc for LogicNode and tighten LowForm-only constraint
(#1657) Fix/update a few Scaladoc links
(#1662) Limit recursion (and reduce total work) in CheckWidths
(#1668) Bump Mima check to 1.2.6
(#1673) Speed up ExpandWhens for very large designs
(#1676) Use Travis Workspaces
(#1708) Add support for ValidIf to ProtoBuf [de]serialization
(#1714) Don't Dedup modules if it would change semanticS