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FIRRTL v1.4.0
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@jackkoenig jackkoenig released this 07 Oct 00:26
v1.4.0
52337d9

Highlights

  • Inline Boolean Expressions (#1817)

Boolean expressions that share a common source locator line will now be inlined in the emitted Verilog.
This can be disabled with --pretty:no-expr-inlining (#1869)

  • Annotations no longer prevent Deduplication (#1539)

Deduplication will turn annotations into instance targets, disambiguating annotations that differ between different instances of the same module. This is the first time that instance target behavior is used extensively and may cause problems in custom transforms.

  • Custom Serialization of Annotations (#1277)

This adds an Annotation mix-in, CustomFileEmission, that allows an annotation to declare how it should be serialized to a file.

  • Avoid repeated inlining in FlattenRegUpdate (#1727)

FIRRTL no longer creates and emits unreachable paths in if-else logic.

  • Propagate source locators to register update always blocks (#1743)

Source locators are now present in emitted always blocks. Source locators are also now more accurate for ternary operators and if-else blocks that derive from when blocks.

  • Relicensed to Apache 2.0 (#1901)
  • Add support for Scala 2.13 (#1796) - Note that Chisel does not yet support Scala 2.13

Deprecations

  • Deprecate support for Scala 2.11 (#1842)
  • Deprecate PreservesAll trait, Remove Usages (#1700)
  • Deprecate CompilerAnnotation (#1870)
  • Deprecate Uniquify (it's now part of LowerTypes) (#1856)
  • Deprecate more firrtl.Compiler methods (#1791)
  • Deprecate InstanceGraph in favor of InstanceKeyGraph (#1800)
  • Deprecating BackendCompilationUtilities trait for object (#1575)

API Modifications

  • when-otherwise scopes are now checked (#1528)

This is not really an API modification but code that formerly was accepted will now be rejected.

  • Make StageOption Unserializable (#1891)

The StageOption annotations will no longer be serialized in output annotation files. In particular, this includes TargetDirAnnotation.

  • Don't use ResolvedAnnotationPaths in ConstProp nor DCE (#1896)

Const Prop and DCE will preserve deduplication even if instances of the same module have differing "dont touch" annotations.

  • RenameMap: remove implicit rename chaining (#1591)
  • Remove Left Over References to Gender in Code (#1752)
  • Remove LegacyAnnotation and [most] MoultingYaml, Remove all uses of ConvertLegacyAnnotations (#1833)
  • Error on ExtModules w/ same defname, different ports (#1734)

Fixes

  • Async reset tieoff bug (#1854)
  • Legalize mem clocks (#1883)
  • Fix Uniquify bug and improve ReplaceSeqMems transforms (#1855)
  • Emit parentheses in Verilog for nested unary ops (#1865)
  • FlattenSpec: flattening a module with no instances is now a no-op (#1868)
  • Add some missing transform invalidations (#1541)
  • Make WrappedTransform work with --class-log-level (#1640)
  • Set prerequisite of -X high to MinimalHighForm (restores FIRRTL 1.2 behavior) (#1704)
  • Mask bits when propagating bitwise ops (#1745)
  • Fix reduction op bug ConstantPropagation (#1746)
  • Make TopWiringTransform run before LowerTypes (#1750)
  • Make InferWidths thread safe (#1775)
  • Update negative literal emission (#1782)
  • Fix sign extension issue in Emitter add sign-extend const-prop test (#1785)
  • WiringTransform: fix non-determinism (#1799)
  • Fixed typo in fixed-point type parameter examples (#1816)
  • Make Utils.expandRef actually return intermediate expressions per API docs (#1624)
  • Fix RemoveIntervals invalidations (#1689)
  • Add support for ValidIf to ProtoBuf [de]serialization (#1707)
  • Don't Dedup modules if it would change semantics (#1713)
  • Fix parsing of info on multi-line registers (#1735)
  • RemoveWires: improve dependencies and declare ResolveKinds as an invalidation (#1797)

Feature

  • Group _RAND_# declarations and guard with ifdef in emitted Verilog (#1548)
  • Better error messages for unserializable annotations (#1885)
  • Cleanup Named Targets (#1311)
  • Apply Scalafmt Rewriting (#1852)
  • Support Memory Initialization for Simulation and FPGA Flows (#1645)
  • Canonicalize init of regs with zero as reset in RemoveReset (#1627)
  • Refactor ManipulateNames to use Target, add --change-name-case <lower|upper> option (#1638)
  • Move Verilog initialization code to end of module (#1613)
  • Add firrtl.stage.Forms.AssertsRemoved for new formal transforms (#1754)
  • Add macros around Verilog initial blocks (#1550)
  • Constant Prop Reduction Operations of Literals (#1558)
  • Add LegalizeAndReductionsTransform (#1556) Workaround for https://github.com/verilator/verilator#2300
  • Add basic transform benchmarking infrastructure and speed up Resolve Kinds (#1475)
  • Do not throw NonFatal exceptions during annotation logging (#1639)
  • Add support for Verilog attributes (#1643)
  • Merge WIR and IR (#1649)
  • Add experimental SMT Backend (#1826)
  • Add mapString method to ir.Port (#1655)
  • Limit recursion (and reduce total work) in CheckWidths (#1646)
  • Speed up ExpandWhens for very large designs (#1666)
  • Build ArrayBuffers in Block.mapStmt (#1669)
  • Speed up CheckHighForm (#1582)
  • Have AppendInfo use MultiInfo, rather than appending with : (#1580)
  • Don't try deduplicating the main module of a circuit (#1594)
  • consolidated wire+assign to just wire, with expression inlined (#1600)
  • Speed up InferTypes and CInferTypes (#1601)
  • Speed up Deduplication, Remove accidental hashing of all Modules in Dedup (#1602)
  • Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)
  • Add scaladoc for LogicNode and tighten LowForm-only constraint in CheckCombLoops (#1635)
  • Compiler: demote compile time logging to info-level instead of error (#1685)
  • Fix determinism in dependency manager (#1686)
  • Store FileInfo string in escaped format (#1690)
  • Add faster IR serializer (#1694)
  • Emit verification node message as Verilog comment (#1712)
  • Batch renames in LowerTypes (#1718)
  • Enable flow from assert to print + stop (#1725)
  • Use structural sha256 hash in Deduplication instead of agnostify and serialize (#1731)
  • Faster dedup instance graph (#1732)
  • Add Expression Fuzzer for testing FIRRTL itself (#1741)
  • Add Firrtl plugin info for intellij platform (#1547)
  • Strip dependencies from BlackBoxSourceHelper (#1840)

FIRRTL specification changes

  • Explicitly disallow shadowing of component names (#1749)
  • Clarify spec definition of indentation and when/else indentation (#1565)
  • Fix typos (#1626) (#1564)

Miscellany

  • Add parse_firrtl_transform_log utility script (#1543)
  • Add find_heap_bound.py script for finding minimum heap size (#1648)
  • Bump to Scala 2.12.12 (#1847)
  • Update antlr4-runtime to 4.7.2 (#1720)
  • Update json4s-native to 3.6.9 (#1692)
  • Update moultingyaml to 0.4.2 (#1480)
  • Update protoc-jar to 3.11.4 (#1434)
  • Update sbt to 1.3.10 (#1529)
  • Update sbt-buildinfo to 0.10.0 (#1529)
  • Update sbt-scalafix to 0.9.15 (#1529)
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