bsp: cortexr52: Use PMU as default timer for Cortex-R52

Cortex-R52 is currently using global timer as its default sleep timer
but inorder to use it, R52 boot code need to configure it through LPD time
stamp generator and in some scenarios this can be protected from R52.
Hence use pmu as its default sleep timer but still provide configuration
option to override it with global timer as per their need. Also when pmu
counter is being used for sleep, user need to ensure that they dont reset
or disable pmu counters.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>
Acked-by: Mubin Sayyed <mubin.sayyed@amd.com>

lib/bsp/standalone/data/standalone.tcl

@@ -1,6 +1,6 @@
 ##############################################################################
 # Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
-# Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+# Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 # SPDX-License-Identifier: MIT
 #
 # MODIFICATION HISTORY:
@@ -91,6 +91,8 @@
 #                     copy appropriate files based on processor and SoC.
 # 9.1   ml   10/08/23 Updated tcl not to set coresight as stdout/stdin for
 #                     non ARM based processors.
+# 9.1   dp   03/26/24 Update tcl to use pmu as sleep timer by default for R52
+#                     and also provide an option to choose global timer.
 ##############################################################################
 
 # ----------------------------------------------------------------------------
@@ -1115,16 +1117,22 @@ proc xsleep_timer_config {proctype os_handle file_handle} {
 
     set sleep_timer [common::get_property CONFIG.sleep_timer $os_handle ]
 	set is_versal [hsi::get_cells -hier -filter {IP_NAME=="psv_cortexa72" || IP_NAME=="psxl_cortexa78" || IP_NAME=="psx_cortexa78"}]
-	if { $sleep_timer == "ps7_globaltimer_0" || $sleep_timer == "psu_iou_scntr" || $sleep_timer == "psu_iou_scntrs" || $sleep_timer == "psv_iou_scntr" || $sleep_timer == "psv_iou_scntrs"} {
+	if { $sleep_timer == "ps7_globaltimer_0" || $sleep_timer == "psu_iou_scntr" || $sleep_timer == "psu_iou_scntrs" || $sleep_timer == "psv_iou_scntr" || $sleep_timer == "psv_iou_scntrs" || $sleep_timer == "psx_lpd_systmr_ctrl" } {
 		if { $proctype == "psu_cortexr5" ||  $proctype == "psv_cortexr5"} {
 			error "ERROR: $proctype does not support $sleep_timer "
 		}
+      if { $proctype == "psx_cortexr52" && $sleep_timer == "psx_lpd_systmr_ctrl" } {
+         puts $file_handle "#define CONFIG_R52_USE_LPD_SYS_TMR"
+      }
     } elseif { $sleep_timer == "none" } {
 		if { $proctype == "psu_cortexr5" || $proctype == "psv_cortexr5" || $proctype == "psxl_cortexr52" || $proctype == "psx_cortexr52"} {
 			set is_ttc_present 0
 			set periphs [hsi::get_cells -hier -filter {IP_NAME==ps7_ttc || IP_NAME==psu_ttc || IP_NAME==psv_ttc || IP_NAME==psxl_ttc || IP_NAME==psx_ttc}]
 			set periphs [lsort -decreasing $periphs]
-                        set en_pmu_sleep_timer [common::get_property CONFIG.pmu_sleep_timer $os_handle ]
+         set en_pmu_sleep_timer [common::get_property CONFIG.pmu_sleep_timer $os_handle ]
+         if { $proctype == "psxl_cortexr52" || $proctype == "psx_cortexr52"} {
+             set en_pmu_sleep_timer "true"
+         }
 
 			foreach periph $periphs {
 				set base_addr [get_base_value $periph]

lib/bsp/standalone/src/arm/cortexr5/gcc/xil-crt0.S

@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
-* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* Copyright (c) 2023 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 /*****************************************************************************/
@@ -43,6 +43,8 @@
 *                     enabled for freertos r52 bsp.
 * 9.0   mus  07/12/23 Fix SDT flow for CortexR52. Code related to CortexR5 has
 *                     been moved to CortexR5 related flag.
+* 9.1   dp   03/26/24 Update the #ifdef check to invoke XTime_StartTimer() only when
+*                     CONFIG_R52_USE_LPD_SYS_TMR is defined.
 * </pre>
 *
 ******************************************************************************/
@@ -168,7 +170,7 @@ noaccess:
 
 	/* configure the timer if TTC is present */
 #ifndef XPAR_XILTIMER_ENABLED
-#if defined (ARMR52) && ((defined(FREERTOS_BSP)) || (defined(XSLEEP_TIMER_IS_DEFAULT_TIMER)))
+#if defined (CONFIG_R52_USE_LPD_SYS_TMR)
 	bl XTime_StartTimer
 #elif defined (SLEEP_TIMER_BASEADDR)
     bl XTime_StartTTCTimer

lib/bsp/standalone/src/arm/cortexr5/sleep.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
-* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -41,6 +41,8 @@
 * 			  to void to fix misra_c_2012_rule_17_7 violation.
 * 8.0   mus  02/24/22    Updated sleep_R5 to support CortexR52 processor.
 * 9.0   ml   03/03/23    add description and remove comments to fix doxygen warnings.
+* 9.1   dp   03/26/24    Use global timer only when CONFIG_R52_USE_LPD_SYS_TMR is
+*                        defined for R52. By default, it uses PMU as sleep timer.
 * </pre>
 *
 ******************************************************************************/
@@ -75,7 +77,7 @@
 ****************************************************************************/
 void sleep_R5(u32 seconds)
 {
-#if defined (ARMR52)
+#if defined (CONFIG_R52_USE_LPD_SYS_TMR)
 	XTime tEnd, tCur;
 
 	tCur = arch_counter_get_cntvct();

lib/bsp/standalone/src/arm/cortexr5/usleep.c

@@ -1,5 +1,6 @@
 /******************************************************************************
 * Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2024 Advanced Micro Devices, Inc. All Rights Reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -40,6 +41,8 @@
 * 8.0   mus  02/24/22    Updated usleep_R5 to support CortexR52 processor.
 * 8.0	sk	 03/02/22 Update usleep_R5 argument type to fix misra_c_2012_
 * 			  directive_4_6 violation.
+* 9.1   dp   03/26/24    Use global timer only when CONFIG_R52_USE_LPD_SYS_TMR is
+*                        defined for R52. By default, it uses PMU as sleep timer.
 *
 * </pre>
 *
@@ -82,7 +85,7 @@
 
 void usleep_R5(ULONG useconds)
 {
-#if defined (ARMR52)
+#if defined (CONFIG_R52_USE_LPD_SYS_TMR)
         XTime tEnd, tCur;
 
         tCur = arch_counter_get_cntvct();

lib/bsp/standalone/src/arm/cortexr5/xtime_l.c

@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
-* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
+* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -41,6 +41,8 @@
 *                        Cortex-R52.
 * 9.0   asa    07/07/23  Made changes to include XTime_StartTimer for
 *                        r52 freertos bsp.
+* 9.1   dp   03/26/24    Use global timer only when CONFIG_R52_USE_LPD_SYS_TMR is
+*                        defined for R52. By default, it uses PMU as sleep timer.
 *
 * </pre>
 *
@@ -64,7 +66,7 @@
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/
-#if defined (ARMR52) && ((defined(FREERTOS_BSP)) || (defined(XSLEEP_TIMER_IS_DEFAULT_TIMER)))
+#if defined (CONFIG_R52_USE_LPD_SYS_TMR)
 
 #define LPD_RST_TIMESTAMP  0xEB5E035CU
 /**
@@ -90,12 +92,12 @@ void XTime_StartTimer(void)
 }
 #endif
 
-#if defined(XSLEEP_TIMER_IS_DEFAULT_TIMER) && defined(ARMR52)
+#if defined(CONFIG_R52_USE_LPD_SYS_TMR)
 #pragma message ("For the sleep routines, global timer is used")
 #elif defined (SLEEP_TIMER_BASEADDR)
 #pragma message ("For the sleep routines, TTC3/TTC2 is used")
 #elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
-#pragma message ("For the sleep routines, PMU cycle counter is used")
+#pragma message ("For the sleep routines, PMU cycle counter is used, dont reset/disable the pmu counters")
 #else
 #pragma message ("For the sleep routines, machine cycles are used")
 #endif
@@ -135,7 +137,7 @@ void XTime_SetTime(XTime Xtime_Global)
 ****************************************************************************/
 void XTime_GetTime(XTime *Xtime_Global)
 {
-#if defined(XSLEEP_TIMER_IS_DEFAULT_TIMER) && defined(ARMR52)
+#if defined(CONFIG_R52_USE_LPD_SYS_TMR)
 	*Xtime_Global = arch_counter_get_cntvct();
 #elif defined (SLEEP_TIMER_BASEADDR)
 	*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +

lib/bsp/standalone/src/arm/cortexr5/xtime_l.h

@@ -1,6 +1,6 @@
 /******************************************************************************
 * Copyright (c) 2014 - 2022 Xilinx, Inc.  All rights reserved.
-* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
+* Copyright (c) 2022 - 2024 Advanced Micro Devices, Inc. All rights reserved.
 * SPDX-License-Identifier: MIT
 ******************************************************************************/
 
@@ -38,6 +38,9 @@
 *                        Cortex-R52.
 * 9.0   asa    07/07/23  Made changes to include bspconfig.h and update
 *                        macros checks for r52 freertos bsp use case.
+* 9.1   dp   03/26/24    Use global timer only when CONFIG_R52_USE_LPD_SYS_TMR is
+*                        defined for R52. By default, it uses PMU as sleep timer.
+*                        Update COUNTS_PER_SECOND accordingly.
 * </pre>
 *
 ******************************************************************************/
@@ -58,7 +61,7 @@ extern "C" {
 #include "xparameters.h"
 #include "bspconfig.h"
 /***************** Macros (Inline Functions) Definitions *********************/
-#if defined (ARMR52)
+#if defined(CONFIG_R52_USE_LPD_SYS_TMR)
 /* TODO: Taken from ARMv8 32 bit BSP, check if we can keep it in some common location */
 static inline u64 arch_counter_get_cntvct(void)
  {
@@ -68,13 +71,12 @@ static inline u64 arch_counter_get_cntvct(void)
   }
 #endif
 /************************** Constant Definitions *****************************/
-
-#if defined (ARMR52)
-#define COUNTS_PER_SECOND     XPAR_CPU_CORTEXR52_0_TIMESTAMP_CLK_FREQ
+#if defined(CONFIG_R52_USE_LPD_SYS_TMR)
+#define COUNTS_PER_SECOND  XPAR_CPU_CORTEXR52_0_TIMESTAMP_CLK_FREQ
 #elif defined (SLEEP_TIMER_BASEADDR)
-
 #define COUNTS_PER_SECOND				SLEEP_TIMER_FREQUENCY
-
+#elif defined (ARMR52)
+#define COUNTS_PER_SECOND      ((XPAR_CPU_CORTEXR52_0_CPU_CLK_FREQ_HZ + 32)/ 64)
 #else
 #define ITERS_PER_SEC  ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2)/ 4)
 #define ITERS_PER_USEC  ((XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ + 2000000)/ 4000000)
@@ -92,12 +94,12 @@ static inline u64 arch_counter_get_cntvct(void)
 
 #define IRQ_FIQ_MASK 	0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
 
-#if defined (ARMR52) && ((defined(FREERTOS_BSP)) || (defined(XSLEEP_TIMER_IS_DEFAULT_TIMER)))
+#if defined (CONFIG_R52_USE_LPD_SYS_TMR)
 #pragma message ("For the sleep routines, global timer is used")
 #elif defined (SLEEP_TIMER_BASEADDR)
 #pragma message ("For the sleep routines, TTC3/TTC2 is used")
 #elif !defined (DONT_USE_PMU_FOR_SLEEP_ROUTINES)
-#pragma message ("For the sleep routines, PMU cycle counter is used")
+#pragma message ("For the sleep routines, PMU cycle counter is used, dont reset/disable the pmu counters")
 #else
 #pragma message ("For the sleep routines, machine cycles are used")
 #endif