Merge branch 'master' into feature_configure_and_enable_the_pll

.github/workflows/RED-V_SiFive_RISC-V_FE310_SoC.yml

@@ -5,40 +5,70 @@ on:
       - '**'
   pull_request:
 jobs:
-  target-gcc-riscv64-unknown-elf:
-    runs-on: ubuntu-22.04
+  target-gcc-riscv32-unknown-elf:
+    runs-on: ubuntu-latest
     defaults:
       run:
         shell: bash
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           fetch-depth: '0'
       - name: update-tools
         run: |
-          wget --no-check-certificate https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-          tar -xvzf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-      - name: target-riscv64-unknown-elf
+          wget --no-check-certificate https://buildbot.embecosm.com/job/riscv32-gcc-ubuntu2204-release/10/artifact/riscv32-embecosm-ubuntu2204-gcc13.2.0.tar.gz
+          tar -xzf riscv32-embecosm-ubuntu2204-gcc13.2.0.tar.gz
+        working-directory: ./
+      - name: target-riscv32-unknown-elf
         run: |
-          PATH=./riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin:$PATH
+          PATH=./riscv32-embecosm-ubuntu2204-gcc13.2.0/bin:$PATH
+          echo 'query compiler version'
+          riscv32-unknown-elf-g++ -v
           bash ./Rebuild.sh
           ls -la ./Output/Blinky_RedV_FE310.hex
-  target-gcc-riscv64-unknown-elf-cmake:
-    runs-on: ubuntu-22.04
+  target-gcc-riscv32-unknown-elf-cmake:
+    runs-on: ubuntu-latest
     defaults:
       run:
         shell: bash
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
         with:
           fetch-depth: '0'
       - name: update-tools
         run: |
-          wget --no-check-certificate https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-          tar -xvzf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
-      - name: target-riscv64-unknown-elf
+          wget --no-check-certificate https://buildbot.embecosm.com/job/riscv32-gcc-ubuntu2204-release/10/artifact/riscv32-embecosm-ubuntu2204-gcc13.2.0.tar.gz
+          tar -xzf riscv32-embecosm-ubuntu2204-gcc13.2.0.tar.gz
+        working-directory: ./
+      - name: target-riscv32-unknown-elf
         run: |
           mkdir -p Output && cd Output
-          PATH=../riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin:$PATH
+          PATH=../riscv32-embecosm-ubuntu2204-gcc13.2.0/bin:$PATH
+          echo 'query compiler version'
+          riscv32-unknown-elf-g++ -v
           cmake -DCMAKE_TOOLCHAIN_FILE=../cmake/toolchain-unix.cmake .. && make
           ls -la ./Blinky_RedV_FE310.hex
+  target-gcc-riscv32-unknown-elf-macos:
+    runs-on: macos-latest
+    defaults:
+      run:
+        shell: bash
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          fetch-depth: '0'
+      - name: update-tools
+        run: |
+          wget --no-check-certificate https://buildbot.embecosm.com/job/riscv32-gcc-macos-release/19/artifact/riscv32-embecosm-macos-gcc13.2.0.dmg
+          hdiutil attach ./riscv32-embecosm-macos-gcc13.2.0.dmg
+          mkdir -p ./riscv32-embecosm-macos-gcc13.2.0
+          cp -rv /Volumes/riscv32-embecosm-macos-gcc13.2.0/riscv32-embecosm-macos-gcc13.2.0 .
+        working-directory: ./
+      - name: target-riscv32-unknown-elf
+        run: |
+          ls -la ./riscv32-embecosm-macos-gcc13.2.0/bin
+          PATH="./riscv32-embecosm-macos-gcc13.2.0/bin:$PATH"
+          echo 'query compiler version'
+          riscv32-unknown-elf-g++ -v
+          bash ./Rebuild.sh
+          ls -la ./Output/Blinky_RedV_FE310.hex

Code/Mcal/riscv-csr.h

@@ -9,6 +9,14 @@
 #ifndef RISCV_CSR_H
 #define RISCV_CSR_H
 
+#if defined(__GNUC__)
+#if defined(__cplusplus)
+asm(".option arch, +zicsr");
+#else
+__asm(".option arch, +zicsr");
+#endif
+#endif
+
 #include <stdint.h>
 
 #if __riscv_xlen==32
@@ -23,13 +31,6 @@ typedef uint64_t uint_csr64_t;
 #error "Unknown XLEN"
 #endif
 
-// Test for Zicsr extension, if relevant
-#if defined(__riscv_arch_test)
-#if !defined(__riscv_zicsr)
-#error "-march must include zicsr to access CSRs" 
-#endif
-#endif
-
 /*******************************************
  * misa - MRW - Machine ISA 
  */

Code/Startup/boot.s

@@ -15,6 +15,8 @@
 
 ******************************************************************************************/
 
+.option arch, +zicsr
+
 .file "boot.s"
 
 /*******************************************************************************************

Code/Startup/intvect.c

@@ -18,6 +18,7 @@
 //=====================================================================================================
 // Includes
 //=====================================================================================================
+#include "FE310.h"
 #include "riscv-csr.h"
 #include "Platform_Types.h"
 
@@ -26,6 +27,7 @@
 //=====================================================================================================
 static void UndefinedHandler(void);
 void DirectModeInterruptHandler(void) __attribute__ ((interrupt ("machine")));
+void Isr_MachineExternalInterrupt(void);
 
 void Isr_InstructionAddressMisaligned (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_InstructionAccessFault       (void) __attribute__((weak, alias("UndefinedHandler")));
@@ -39,7 +41,6 @@ void Isr_EnvironmentCallFromUmode     (void) __attribute__((weak, alias("Undefin
 void Isr_EnvironmentCallFromMmode     (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_MachineSoftwareInterrupt     (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_MachineTimerInterrupt        (void) __attribute__((weak, alias("UndefinedHandler")));
-void Isr_MachineExternalInterrupt     (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_WATCHDOG_IRQn                (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_RTC_IRQn                     (void) __attribute__((weak, alias("UndefinedHandler")));
 void Isr_UART0_IRQn                   (void) __attribute__((weak, alias("UndefinedHandler")));
@@ -212,8 +213,8 @@ static void UndefinedHandler(void)
 void DirectModeInterruptHandler(void)
 {
   /* get the exception cause number */
-  uint32 mcause = csr_read_mcause();
-  uint32 idx    = (mcause & ((1UL<< 10u) - 1u)) + 12 * (mcause >> 31u);
+  const uint32 mcause = csr_read_mcause();
+  const uint32 idx    = (mcause & ((1UL<< 10u) - 1u)) + 12 * (mcause >> 31u);
 
   if(idx < 24u)
   {
@@ -223,3 +224,24 @@ void DirectModeInterruptHandler(void)
 
 }
 
+//-----------------------------------------------------------------------------------------
+/// \brief  
+///
+/// \param  
+///
+/// \return 
+//-----------------------------------------------------------------------------------------
+void Isr_MachineExternalInterrupt(void)
+{
+  /* get the PLIC pending interrupt ID */
+  const uint32 IntId = PLIC->claim;
+
+  if(IntId < 52u)
+  {
+    /* call the appropriate interrupt service routine */
+    PLIVT[IntId]();
+  }
+
+  /* set the interrupt as completed */
+   PLIC->claim = IntId;
+}

LICENSE_1_0.txt

@@ -0,0 +1,23 @@
+Boost Software License - Version 1.0 - August 17th, 2003
+
+Permission is hereby granted, free of charge, to any person or organization
+obtaining a copy of the software and accompanying documentation covered by
+this license (the "Software") to use, reproduce, display, distribute,
+execute, and transmit the Software, and to prepare derivative works of the
+Software, and to permit third-parties to whom the Software is furnished to
+do so, all subject to the following:
+
+The copyright notices in the Software and this entire statement, including
+the above license grant, this restriction and the following disclaimer,
+must be included in all copies of the Software, in whole or in part, and
+all derivative works of the Software, unless such copies or derivative
+works are solely in the form of machine-executable object code generated by
+a source language processor.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT
+SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE SOFTWARE BE LIABLE
+FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE,
+ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.

Makefile

@@ -26,7 +26,7 @@ SRC_DIR    = Code
 # Toolchain
 ############################################################################################
 
-TOOLCHAIN = riscv64-unknown-elf
+TOOLCHAIN = riscv32-unknown-elf
 AS        = $(TOOLCHAIN)-g++
 CC        = $(TOOLCHAIN)-g++
 CPP       = $(TOOLCHAIN)-g++
@@ -59,7 +59,7 @@ VERBOSE_GCC = -frecord-gcc-switches -fverbose-asm
 # Target's Compiler flags
 ############################################################################################
 
-ARCH = -mcpu=sifive-e31 -mabi=ilp32 -msmall-data-limit=0 -falign-functions=4
+ARCH = -mcpu=sifive-e31 -mabi=ilp32 -march=rv32imac -msmall-data-limit=0 -falign-functions=4
 
 ############################################################################################
 # C Compiler flags

README.md

@@ -2,7 +2,12 @@ RED-V_SiFive_RISC-V_FE310_SoC
 ==================
 Bare metal programming on the RED-V Thing Plus board (SiFive RISC-V FE310 SoC).
 
-[![Build Status](https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/actions/workflows/RED-V_SiFive_RISC-V_FE310_SoC.yml/badge.svg)](https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/actions)
+<p align="center">
+    <a href="https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/actions">
+        <img src="https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/actions/workflows/RED-V_SiFive_RISC-V_FE310_SoC.yml/badge.svg" alt="Build Status"></a>
+    <a href="https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/blob/master/LICENSE_1_0.txt">
+        <img src="https://img.shields.io/badge/license-BSL%201.0-blue.svg" alt="Boost Software License 1.0"></a>
+</p>
 
 This repository implements an entirely manually-written, pure
 _bare_ _metal_ Blinky Project for the SiFive RISC-V FE310 SoC
@@ -14,11 +19,13 @@ Features include:
   - blinky LED show with adjustable frequency,
   - implementation in C99 with absolute minimal use of assembly.
 
-A clear and easy-to-understand build system based on GNUmake
-completes this fun and educational project.
+Clear and easy-to-understand build systems based on either
+GNUmake or CMake complete this fun and educational project.
 
 This repository provides keen insight on starting up
-a _bare_ _metal_ SiFive RISC-V controller.
+a _bare_ _metal_ SiFive RISC-V controller. It emphasizes
+simplicity and independence from monolithic toolchains
+through its lightweight, self-written implementation.
 
 ## Details on the Application
 
@@ -33,18 +40,22 @@ to provide a rudimentary, visible blinky LED show.
 The timebase for blinky is based on the `mtimer`
 interrupt handler.
 
+Blinky running on the target is shown in the image below.
+
+![](./images/red_five.jpg)
+
 ## Building the Application
 
-Build on `*nix*` is easy using an installed `gcc-riscv64-unknown-elf`
+Build on `*nix*` is easy using `gcc-riscv32-unknown-elf`
 
 Both Make and Cmake can be used to build the Application:
 
 ```sh
 cd RED-V_SiFive_RISC-V_FE310_SoC
 ```
 ### Make
-```
-bash Rebuild.sh
+```sh
+./Rebuild.sh
 ```
 ### CMake
 ```sh
@@ -55,13 +66,20 @@ cmake -DCMAKE_TOOLCHAIN_FILE=../cmake/toolchain-unix.cmake .. && make
 The build results including ELF-file, HEX-mask, MAP-file
 and assembly list file are created in the `Output`directory.
 
-If `gcc-riscv64-unknown-elf` is not installed, it can easily
-be obtained [here](https://github.com/sifive/freedom-tools/releases).
+If `gcc-riscv32-unknown-elf` is not installed, it can easily
+be obtained from [embecosm](https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable).
 Add the path of the RISC-V GCC tools' bin folder to `$PATH`
 in the usual `*nix` way.
 
 ## Continuous Integration
 
 CI runs on pushes and pull-requests with simple
 build(s) including result verification on `ubuntu-latest`
-using GitHub Actions.
+and `macos-latest` using GitHub Actions.
+
+## Licensing
+
+The project code is licensed under BSL with the exception of
+the [register definition file](https://github.com/Embedded-System-Lovers/RED-V_SiFive_RISC-V_FE310_SoC/blob/master/Code/Mcal/riscv-csr.h)
+originally from [five-embedded](https://five-embeddev.com) which
+is licenced under the Unlicense.

cmake/toolchain-unix.cmake

@@ -1,7 +1,7 @@
 set(CMAKE_SYSTEM_NAME             Generic)
 set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
 
-set(TOOLCHAIN          riscv64-unknown-elf)
+set(TOOLCHAIN          riscv32-unknown-elf)
 set(AR                 ${TOOLCHAIN}-ar)
 set(AS                 ${TOOLCHAIN}-as)
 set(CC                 ${TOOLCHAIN}-gcc)