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/****************************************************************************************** | ||
Filename : Clock.c | ||
Core : RV32IMAC | ||
MCU : FE310-G002 (SiFive) | ||
Author : Chalandi Amine | ||
Owner : Chalandi Amine | ||
Date : 11.12.2022 | ||
Description : Clock driver implementation | ||
******************************************************************************************/ | ||
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//===================================================================================================== | ||
// Includes | ||
//===================================================================================================== | ||
#include "FE310.h" | ||
#include "Clock.h" | ||
#include "riscv-csr.h" | ||
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//===================================================================================================== | ||
// Functions prototype | ||
//===================================================================================================== | ||
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//===================================================================================================== | ||
// Macros | ||
//===================================================================================================== | ||
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//===================================================================================================== | ||
// Globals | ||
//===================================================================================================== | ||
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//----------------------------------------------------------------------------------------- | ||
/// \brief | ||
/// | ||
/// \param | ||
/// | ||
/// \return | ||
//----------------------------------------------------------------------------------------- | ||
void FE310_ClockInitialization(void) | ||
{ | ||
/* wait for HFXOSC to be become ready */ | ||
while(!PRCI->hfxosccfg.bit.ready); | ||
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/* select pllref clock (HFXOSC) */ | ||
PRCI->pllcfg.bit.refsel = 1; | ||
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/* divide pllref (HFXOSC) by 2 ==> refr = 8 MHz */ | ||
PRCI->pllcfg.bit.pllr = 1; | ||
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/* multiply refr by 96 ==> vco = 768 MHz */ | ||
PRCI->pllcfg.bit.pllf = 47; | ||
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/* divide vco by 4 ==> pllout = 192 MHz */ | ||
PRCI->pllcfg.bit.pllq = 2; | ||
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/* bypass final pllout divider */ | ||
PRCI->plloutdiv.bit.divby1 = 1; | ||
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/* drive the final hfclk with the PLL output */ | ||
PRCI->pllcfg.bit.sel = 1; | ||
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/* disable pll bypass */ | ||
PRCI->pllcfg.bit.bypass = 0; | ||
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/* wait for pll to lock */ | ||
while(!PRCI->pllcfg.bit.lock); | ||
} |
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Original file line number | Diff line number | Diff line change |
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/****************************************************************************************** | ||
Filename : Clock.h | ||
Core : RV32IMAC | ||
MCU : FE310-G002 (SiFive) | ||
Author : Chalandi Amine | ||
Owner : Chalandi Amine | ||
Date : 11.12.2022 | ||
Description : Clock driver header file | ||
******************************************************************************************/ | ||
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#ifndef __CLOCK_H__ | ||
#define __CLOCK_H__ | ||
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//===================================================================================================== | ||
// Functions prototype | ||
//===================================================================================================== | ||
void FE310_ClockInitialization(void); | ||
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#endif /* __MCU_H__ */ | ||
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