Skip to content
View weidingliu's full-sized avatar
🎯
Focusing
🎯
Focusing
  • Nanjing University of Science and Technology
  • Nanjing & Beijing, China
  • 20:54 - 8h ahead

Organizations

@OpenXiangShan

Block or report weidingliu

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results
Python 10 1 Updated Jan 16, 2025

Open-source high-performance RISC-V processor

Scala 6,115 735 Updated Feb 25, 2025
Python 4 1 Updated Feb 7, 2025

A RISC-V core running Debian (and a LoongArch core running Linux).

Scala 22 4 Updated Feb 26, 2024

🌍 A Collection of Awesome Large Weather Models (LWMs) | AI for Earth (AI4Earth) | AI for Science (AI4Science)

221 28 Updated Feb 20, 2025

Instruction Set Generator initially contributed by Futurewei

C++ 272 62 Updated Oct 17, 2023

LicheeTang 蜂鸟E203 Core

Verilog 190 62 Updated Jul 10, 2019

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

C 400 138 Updated Feb 22, 2025

🎮 A Benchmark and Awesome Collection of Methods for Remote Sensing Image-Text Retrieval (RSITR)| Remote Sensing Cross-Model Retrieval (RSCMR) | Remote Sensing Vision-Lanuage Models (RSVLMs)

50 Updated Mar 30, 2024

GNU toolchain for RISC-V, including GCC

C 3,749 1,214 Updated Jan 20, 2025

upstream: https://github.com/RALC88/gem5

C++ 31 14 Updated May 30, 2023

GPGPU microprocessor architecture

C 2,048 357 Updated Nov 8, 2024

The official repository for the gem5 computer-system architecture simulator.

C++ 1,844 1,324 Updated Feb 24, 2025
C++ 74 32 Updated Feb 25, 2025

Open-source non-blocking L2 cache

Scala 35 22 Updated Feb 25, 2025

Modern co-simulation framework for RISC-V CPUs

C++ 133 71 Updated Feb 25, 2025

Open-source high-performance non-blocking cache

Scala 76 35 Updated Feb 19, 2025

Documentation for XiangShan

Markdown 404 138 Updated Feb 25, 2025

RISC-V Linux Port

C 606 213 Updated Apr 12, 2019

XiangShan Frontend Develop Environment

Shell 52 53 Updated Feb 25, 2025

Mill is a fast build tool that supports Java, Scala, Kotlin and many other languages. 2-4x faster than Gradle and 4-10x faster than Maven for common workflows, Mill aims to make your project’s buil…

Scala 2,339 382 Updated Feb 25, 2025

Vector processor for RISC-V vector ISA

SystemVerilog 113 25 Updated Oct 19, 2020

🦢 [ICMR'23 Oral] Official Code for “Reducing Semantic Confusion: Scene-aware Aggregation Network for Remote Sensing Cross-modal Retrieval”

Python 21 3 Updated Dec 22, 2023

🧀 [ACMMM'23 Oral] Official Code for “A Prior Instruction Representation Framework for Remote Sensing Image-text Retrieval”

Python 29 2 Updated Jan 19, 2024

OpenXuantie - OpenC906 Core

Verilog 337 105 Updated Jun 28, 2024
C 259 99 Updated Feb 25, 2025

A minimal, modularized, and machine-independent hardware abstraction layer

C 472 90 Updated Dec 29, 2024

assembly experiment environment for loongarch

C 19 4 Updated Aug 11, 2022

High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)

Scala 75 5 Updated Aug 29, 2023
Next
Showing results