Merge branch 'gemv-support' of github.com:ucb-bar/gemmini into gemv-s…

…upport merge
ucb-bar · Apr 27, 2024 · 9528af7 · 9528af7
2 parents d80efa6 + 2366a5c
commit 9528af7
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/src/main/scala/gemmini/GemminiISA.scala b/src/main/scala/gemmini/GemminiISA.scala
@@ -178,7 +178,8 @@ object GemminiISA {
   val CONFIG_EX_RS1_CMD_TYPE_WIDTH = 2
   val CONFIG_EX_RS1_DATAFLOW_WIDTH = 1
   val CONFIG_EX_RS1_ACTIVATION_WIDTH = 2
-  val CONFIG_EX_RS1_SPACER0_WIDTH = (7 - 2 - 1 - 2)
+  val CONFIG_EX_RS1_SPACER0_WIDTH = (7 - 2 - 1 - 2 - 1)
+  val CONFIG_EX_RS1_IS_GEMV_WIDTH = 1
   val CONFIG_EX_RS1_SET_ONLY_STRIDES_WIDTH = 1
   val CONFIG_EX_RS1_A_TRANSPOSE_WIDTH = 1
   val CONFIG_EX_RS1_B_TRANSPOSE_WIDTH = 1
@@ -194,6 +195,7 @@ object GemminiISA {
     val b_transpose = UInt(CONFIG_EX_RS1_B_TRANSPOSE_WIDTH.W)
     val a_transpose = UInt(CONFIG_EX_RS1_A_TRANSPOSE_WIDTH.W)
     val set_only_strides = UInt(CONFIG_EX_RS1_SET_ONLY_STRIDES_WIDTH.W)
+    val is_gemv = UInt(CONFIG_EX_RS1_IS_GEMV_WIDTH.W)
     val _spacer0 = UInt(CONFIG_EX_RS1_SPACER0_WIDTH.W)
     val activation = UInt(CONFIG_EX_RS1_ACTIVATION_WIDTH.W)
     val dataflow = UInt(CONFIG_EX_RS1_DATAFLOW_WIDTH.W)