ADD: submodule tacit & tacit decoder

.github/scripts/check-commit.sh

@@ -46,7 +46,7 @@ search () {
 }
 
 
-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "tacit")
 dir="generators"
 branches=("master" "main" "dev")
 search

.gitmodules

@@ -154,3 +154,9 @@
 [submodule "generators/vexiiriscv"]
 	path = generators/vexiiriscv
 	url = https://github.com/ucb-bar/vexiiriscv-tile.git
+[submodule "software/tacit_decoder"]
+	path = software/tacit_decoder
+	url = https://github.com/ucb-bar/tacit_decoder.git
+[submodule "generators/tacit"]
+	path = generators/tacit
+	url = https://github.com/ucb-bar/tacit.git

build.sbt

@@ -158,7 +158,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
     dsptools, rocket_dsp_utils,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
     constellation, mempress, barf, shuttle, caliptra_aes, rerocc,
-    compressacc, saturn, ara, firrtl2_bridge, vexiiriscv)
+    compressacc, saturn, ara, firrtl2_bridge, vexiiriscv, tacit)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(
     libraryDependencies ++= Seq(
@@ -253,6 +253,11 @@ lazy val nvdla = (project in file("generators/nvdla"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val tacit = (project in file("generators/tacit"))
+  .dependsOn(rocketchip, shuttle)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
 lazy val caliptra_aes = (project in file("generators/caliptra-aes-acc"))
   .dependsOn(rocketchip, rocc_acc_utils, testchipip)
   .settings(libraryDependencies ++= rocketLibDeps.value)

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -4,6 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
+import freechips.rocketchip.trace._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
@@ -13,6 +14,7 @@ import freechips.rocketchip.devices.tilelink._
 
 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
+  with tacit.CanHaveTraceSinkDMA
   with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
   with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
   with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -115,3 +115,14 @@ class SV48RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithSV48 ++
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
+
+// Rocket with Tacit encoder and trace sinks
+class TacitRocketConfig extends Config(
+  new tacit.WithTraceSinkDMA(1) ++
+  new tacit.WithTraceSinkAlways(0) ++
+  new chipyard.config.WithTraceArbiterMonitor ++
+  new chipyard.config.WithTacitEncoder ++
+  new chipyard.config.WithNPerfCounters(29) ++
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new freechips.rocketchip.rocket.WithNHugeCores(1) ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/ShuttleConfigs.scala

@@ -30,3 +30,13 @@ class GemminiShuttleConfig extends Config(
   new gemmini.DefaultGemminiConfig ++                            // use Gemmini systolic array GEMM accel
   new shuttle.common.WithNShuttleCores ++
   new chipyard.config.AbstractConfig)
+
+// Shuttle with Tacit encoder and trace sinks
+class TacitShuttleConfig extends Config(
+  new tacit.WithTraceSinkDMA(1) ++
+  new tacit.WithTraceSinkAlways(0) ++
+  new chipyard.config.WithTraceArbiterMonitor ++
+  new chipyard.config.WithTacitEncoder ++
+  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
+  new shuttle.common.WithNShuttleCores ++
+  new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/config/fragments/TileFragments.scala

@@ -6,14 +6,17 @@ import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
+import freechips.rocketchip.diplomacy._
 
 import cva6.{CVA6TileAttachParams}
 import sodor.common.{SodorTileAttachParams}
 import ibex.{IbexTileAttachParams}
 import vexiiriscv.{VexiiRiscvTileAttachParams}
 import testchipip.cosim.{TracePortKey, TracePortParams}
 import barf.{TilePrefetchingMasterPortParams}
-
+import freechips.rocketchip.trace.{TraceEncoderParams, TraceCoreParams}
+import tacit.{TacitEncoder}
+import shuttle.common.{ShuttleTileAttachParams}
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
@@ -64,6 +67,46 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   }
 })
 
+// Add a Tacit encoder to each tile
+class WithTacitEncoder extends Config((site, here, up) => {
+   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      traceParams = Some(TraceEncoderParams(
+        encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
+        buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
+          nGroups = 1,
+          xlen = tp.tileParams.core.xLen,
+          iaddrWidth = tp.tileParams.core.xLen
+        ), 
+        bufferDepth = 16,
+        coreStages = 5)(p)),
+        useArbiterMonitor = false
+      )),
+      core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
+    case tp: ShuttleTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      traceParams = Some(TraceEncoderParams(
+        encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
+        buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
+          nGroups = tp.tileParams.core.retireWidth,
+          xlen = tp.tileParams.core.xLen,
+          iaddrWidth = tp.tileParams.core.xLen
+        ), bufferDepth = 16, coreStages = 7)(p)),
+        useArbiterMonitor = false
+      )),
+      core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
+   }
+ })
+
+// Add a monitor to RTL print the sinked packets into a file for debugging
+class WithTraceArbiterMonitor extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true))))
+    case tp: ShuttleTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true))))
+  }
+})
+
 class WithNPMPs(n: Int = 8) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(