FIX: address all PR comments

ucb-bar · Feb 7, 2025 · e6c53a3 · e6c53a3
1 parent 8d408ef
commit e6c53a3
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Showing 5 changed files with 16 additions and 14 deletions.
diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
@@ -46,7 +46,7 @@ search () {
 }
 
 
-submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv")
+submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy" "rerocc" "compress-acc" "saturn" "ara" "vexiiriscv" "tacit")
 dir="generators"
 branches=("master" "main" "dev")
 search

diff --git a/.gitmodules b/.gitmodules
@@ -153,7 +153,7 @@
 	url = https://github.com/ucb-bar/vexiiriscv-tile.git
 [submodule "software/tacit_decoder"]
 	path = software/tacit_decoder
-	url = git@github.com:ucb-bar/tacit_decoder.git
+	url = https://github.com/ucb-bar/tacit_decoder.git
 [submodule "generators/tacit"]
 	path = generators/tacit
-	url = git@github.com:ucb-bar/tacit.git
+	url = https://github.com/ucb-bar/tacit.git
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -116,11 +116,12 @@ class SV48RocketConfig extends Config(
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++
   new chipyard.config.AbstractConfig)
 
-class LTraceEncoderRocketConfig extends Config(
+// Rocket with Tacit encoder and trace sinks
+class TacitRocketConfig extends Config(
   new tacit.WithTraceSinkDMA(1) ++
   new tacit.WithTraceSinkAlways(0) ++
-  new chipyard.config.WithArbiterMonitor ++
-  new chipyard.config.WithLTraceEncoder ++
+  new chipyard.config.WithTraceArbiterMonitor ++
+  new chipyard.config.WithTacitEncoder ++
   new chipyard.config.WithNPerfCounters(29) ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.rocket.WithNHugeCores(1) ++

diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala
@@ -43,11 +43,12 @@ class GemminiShuttleConfig extends Config(
   new shuttle.common.WithNShuttleCores ++
   new chipyard.config.AbstractConfig)
 
+// Shuttle with Tacit encoder and trace sinks
 class TacitShuttleConfig extends Config(
-  // new tacit.WithTraceSinkDMA(1) ++
+  new tacit.WithTraceSinkDMA(1) ++
   new tacit.WithTraceSinkAlways(0) ++
-  new chipyard.config.WithArbiterMonitor ++
-  new chipyard.config.WithLTraceEncoder ++
+  new chipyard.config.WithTraceArbiterMonitor ++
+  new chipyard.config.WithTacitEncoder ++
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new shuttle.common.WithNShuttleCores ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -67,14 +67,14 @@ class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
   }
 })
 
-class WithLTraceEncoder extends Config((site, here, up) => {
+// Add a Tacit encoder to each tile
+class WithTacitEncoder extends Config((site, here, up) => {
    case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
      case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       traceParams = Some(TraceEncoderParams(
         encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
         buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
           nGroups = 1,
-          iretireWidth = 1,
           xlen = tp.tileParams.core.xLen,
           iaddrWidth = tp.tileParams.core.xLen
         ), 
@@ -88,17 +88,17 @@ class WithLTraceEncoder extends Config((site, here, up) => {
         encoderBaseAddr = 0x3000000 + tp.tileParams.tileId * 0x1000,
         buildEncoder = (p: Parameters) => LazyModule(new TacitEncoder(new TraceCoreParams(
           nGroups = tp.tileParams.core.retireWidth,
-          iretireWidth = 1,
           xlen = tp.tileParams.core.xLen,
           iaddrWidth = tp.tileParams.core.xLen
-        ), bufferDepth = 16, coreStages = 5)(p)),
+        ), bufferDepth = 16, coreStages = 7)(p)),
         useArbiterMonitor = false
       )),
       core = tp.tileParams.core.copy(enableTraceCoreIngress=true)))
    }
  })
 
-class WithArbiterMonitor extends Config((site, here, up) => {
+// Add a monitor to RTL print the sinked packets into a file for debugging
+class WithTraceArbiterMonitor extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
     case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
       traceParams = Some(tp.tileParams.traceParams.get.copy(useArbiterMonitor = true))))