fixes to various setups

ucb-bar · Feb 28, 2024 · 5254a1f · 5254a1f
1 parent 6a9a07e
commit 5254a1f
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Showing 3 changed files with 16 additions and 33 deletions.
diff --git a/soc/setup.sh b/soc/setup.sh
@@ -97,33 +97,6 @@ for ((i=0;i<${#sources[@]};++i)); do
     ln -s "${sources[$i]}" "${destinations[$i]}"
 done
 
-# # Copy scala files
-# cp ${SCALA_DIR}/AirSimIO.scala ${CHIPYARD_DIR}/generators/chipyard/src/main/scala/example/
-# cp ${SCALA_DIR}/IOBinders.scala ${CHIPYARD_DIR}/generators/chipyard/src/main/scala/
-# cp ${SCALA_DIR}/BridgeBinders.scala ${CHIPYARD_DIR}/generators/firechip/src/main/scala/
-# cp ${SCALA_DIR}/DigitalTop.scala ${CHIPYARD_DIR}/generators/chipyard/src/main/scala/
-# cp ${SCALA_DIR}/AbstractConfig.scala ${CHIPYARD_DIR}/generators/chipyard/src/main/scala/config/
-# cp ${SCALA_DIR}/AirSimBridge.scala  ${FIRESIM_DIR}/sim/firesim-lib/src/main/scala/bridges/
-# cp ${SCALA_DIR}/RoSEConfigs.scala ${CHIPYARD_DIR}/generators/chipyard/src/main/scala/config/
-
-# # Copy C++ files
-# cp ${FSIM_CC_DIR}/airsim.cc ${FIRESIM_DIR}/sim/firesim-lib/src/main/cc/bridges/
-# # cp ${FSIM_CC_DIR}/heartbeat.cc ${FIRESIM_DIR}/sim/firesim-lib/src/main/cc/bridges/
-# cp ${FSIM_CC_DIR}/airsim.h ${FIRESIM_DIR}/sim/firesim-lib/src/main/cc/bridges/
-# # cp ${FSIM_CC_DIR}/heartbeat.h ${FIRESIM_DIR}/sim/firesim-lib/src/main/cc/bridges/
-# cp ${FSIM_CC_DIR}/firesim_top.cc ${FIRESIM_DIR}/sim/src/main/cc/firesim/
-
-
-# # Copy simulation configs
-# cp ${ROSE_DIR}/soc/sim/config_runtime_local.yaml        ${FIRESIM_DIR}/deploy/config_runtime.yaml
-# cp ${ROSE_DIR}/soc/sim/config_build_recipes_local.yaml  ${FIRESIM_DIR}/deploy/config_build_recipes.yaml
-# cp ${ROSE_DIR}/soc/sim/config_build_local.yaml          ${FIRESIM_DIR}/deploy/config_build.yaml
-# cp ${ROSE_DIR}/soc/sim/config_hwdb_local.yaml           ${FIRESIM_DIR}/deploy/config_hwdb.yaml
-
-# Copy workload configs
-# cp ${ROSE_DIR}/soc/sim/airsim-driver-fed.json ${FIRESIM_DIR}/deploy/workloads/
-# cp ${ROSE_DIR}/soc/sim/airsim-control-fed.json ${FIRESIM_DIR}/deploy/workloads/
-
 # Init firemarshal submodules
 cd ${FIRESIM_DIR}/sw/firesim-software/
 git checkout ubuntu-add
@@ -143,12 +116,21 @@ lazy val rose = (project in file("generators/rose"))
   .settings(commonSettings)' >> ${CHIPYARD_DIR}/build.sbt
 fi
 
-CHIPYARD_FILE="${CHIPYARD_DIR}/build.sbt"
-
 # Check if 'rose' is already a dependency under lazy val chipyard
-echo "Updating build.sbt"
+echo "Updating cy build.sbt"
 sed -i 's/gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,/gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator, rose,/g' ${CHIPYARD_DIR}/build.sbt
 
+if grep -q "lazy val rose" ${FIRESIM_DIR}/sim/build.sbt; then
+  echo "rose found in firesim/sim sbt, not appending."
+else
+  echo "rose not found in firesim/sim sbt, appending."
+  echo '
+lazy val rose          = ProjectRef(chipyardDir, "rose")
+' >> ${FIRESIM_DIR}/sim/build.sbt
+fi
+echo "Updating fsim build.sbt"
+sed -i 's/.dependsOn(midas, icenet, testchipip, rocketchip_blocks)/.dependsOn(midas, icenet, testchipip, rocketchip_blocks, rose)/g' ${FIRESIM_DIR}/sim/build.sbt
+
 echo "Updating onnxruntime-riscv submodules"
 cd ${ROSE_DIR}
 git submodule update --init --recursive ${ROSE_DIR}/soc/sw/onnxruntime-riscv

diff --git a/soc/src/main/scala/IOBinders.scala b/soc/src/main/scala/IOBinders.scala
@@ -35,6 +35,8 @@ import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
 import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
 import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
 
+import rose.{CanHavePeripheryRoseAdapter, RoseAdapterKey, RoseAdapterParams, RosePortIO}
+
 import scala.reflect.{ClassTag}
 
 object IOBinderTypes {
@@ -516,7 +518,6 @@ class WithTLMemPunchthrough extends OverrideIOBinder({
   }
 })
 
-
 class WithDontTouchPorts extends OverrideIOBinder({
   (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil)
 })

diff --git a/soc/src/main/scala/Ports.scala b/soc/src/main/scala/Ports.scala
@@ -18,7 +18,7 @@ import freechips.rocketchip.subsystem.{MemoryPortParams, MasterPortParams, Slave
 import freechips.rocketchip.devices.debug.{ClockedDMIIO}
 import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.tilelink.{TLBundle}
-import rose.{RosePortIO}
+import rose.{RosePortIO, RoseAdapterParams}
 
 trait Port[T <: Data] {
   val getIO: () => T
@@ -110,5 +110,5 @@ case class JTAGResetPort   (val getIO: () => Reset)
 case class TLMemPort       (val getIO: () => HeterogeneousBag[TLBundle])
     extends Port[HeterogeneousBag[TLBundle]]
 
-case class RoseAdapterPort    (val getIO: () => ClockedIO[RosePortIO], val adapterID: Int)
+case class RoseAdapterPort    (val getIO: () => ClockedIO[RosePortIO], val params: RoseAdapterParams)
     extends Port[ClockedIO[RosePortIO]]