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[MC68000] Refactor instruction table
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tgtakaoka committed Dec 20, 2023
1 parent 1678e5d commit 135ecc5
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Showing 6 changed files with 96 additions and 109 deletions.
36 changes: 18 additions & 18 deletions src/asm_mc68000.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ void emitOprSize(AsmInsn &insn, InsnSize isize) {
case ISZ_WORD:
insn.embed(1 << 6);
break;
case ISZ_QUAD:
case ISZ_LONG:
insn.embed(2 << 6);
break;
default: // ISZ_BYTE
Expand All @@ -122,12 +122,12 @@ void emitOprSize(AsmInsn &insn, InsnSize isize) {
return;
}
if (osize == SZ_ADDR) {
if (isize == ISZ_QUAD)
if (isize == ISZ_LONG)
insn.embed(1 << 6);
return;
}
if (osize == SZ_ADR8) {
if (isize == ISZ_QUAD)
if (isize == ISZ_LONG)
insn.embed(1 << 8);
return;
}
Expand All @@ -136,7 +136,7 @@ void emitOprSize(AsmInsn &insn, InsnSize isize) {
Error AsmMc68000::checkAlignment(AsmInsn &insn, OprSize size, const Operand &op) const {
if (size == SZ_WORD && (op.val32 % 2))
return insn.setError(op, OPERAND_NOT_ALIGNED);
if (size == SZ_QUAD && (op.val32 % 2))
if (size == SZ_LONG && (op.val32 % 2))
return insn.setError(op, OPERAND_NOT_ALIGNED);
return OK;
}
Expand All @@ -149,7 +149,7 @@ void AsmMc68000::emitBriefExtension(
ext |= encodeGeneralRegNo(op.indexReg) << 12;
if (isAddrReg(op.indexReg))
ext |= (1 << 15);
if (op.indexSize == ISZ_QUAD)
if (op.indexSize == ISZ_LONG)
ext |= (1 << 11);
insn.emitOperand16(ext);
}
Expand Down Expand Up @@ -179,7 +179,7 @@ void AsmMc68000::emitRelativeAddr(AsmInsn &insn, AddrMode mode, const Operand &o
void AsmMc68000::emitImmediateData(
AsmInsn &insn, const Operand &op, OprSize size, uint32_t data) const {
switch (size) {
case SZ_QUAD:
case SZ_LONG:
insn.emitOperand32(data);
return;
case SZ_WORD:
Expand All @@ -200,7 +200,7 @@ void AsmMc68000::emitImmediateData(
Config::uintptr_t Operand::offset(const AsmInsn &insn) const {
if (getError())
return 0;
uint8_t len = insn.length();
auto len = insn.length();
if (len == 0)
len = sizeof(Config::opcode_t);
return val32 - (insn.address() + len);
Expand All @@ -214,15 +214,15 @@ Error AsmMc68000::emitEffectiveAddr(
return insn.getError();
}

const int8_t mode_gp = modePos(pos);
const auto mode_gp = modePos(pos);
if (mode_gp >= 0) {
const Config::opcode_t m = EaMc68000::encodeMode(op.mode);
const auto m = EaMc68000::encodeMode(op.mode);
insn.embed(m << mode_gp);
}

const int8_t reg_gp = regPos(pos);
const auto reg_gp = regPos(pos);
if (reg_gp >= 0) {
const Config::opcode_t r = EaMc68000::encodeRegNo(op.mode, op.reg);
const auto r = EaMc68000::encodeRegNo(op.mode, op.reg);
insn.embed(r << reg_gp);
}

Expand Down Expand Up @@ -289,7 +289,7 @@ Error AsmMc68000::emitEffectiveAddr(
emitImmediateData(insn, op, size, op.val32);
break;
case M_LABEL:
if (size == SZ_QUAD || (size == SZ_BYTE && mode == M_REL16))
if (size == SZ_LONG || (size == SZ_BYTE && mode == M_REL16))
insn.setErrorIf(op, ILLEGAL_SIZE);
if (size == SZ_WORD && mode == M_REL8)
mode = M_REL16;
Expand Down Expand Up @@ -320,8 +320,8 @@ void AsmMc68000::emitRegisterList(AsmInsn &insn, const Operand &op, bool reverse
const auto start = parseRegName(a);
if (!isGeneralReg(start))
insn.setErrorIf(p, REGISTER_NOT_ALLOWED);
const uint8_t s = encodeGeneralRegPos(start);
uint8_t e = s;
const auto s = encodeGeneralRegPos(start);
auto e = s;
if (*a == '-') {
++a;
p = a.skipSpaces();
Expand All @@ -332,7 +332,7 @@ void AsmMc68000::emitRegisterList(AsmInsn &insn, const Operand &op, bool reverse
if (e < s)
insn.setErrorIf(UNKNOWN_OPERAND);
}
for (uint8_t i = s; i <= e; i++) {
for (auto i = s; i <= e; i++) {
const auto bm = 1U << i;
if (bits & bm)
insn.setErrorIf(p, DUPLICATE_REGISTER);
Expand Down Expand Up @@ -365,7 +365,7 @@ Error AsmMc68000::parseOperand(StrScanner &scan, Operand &op) const {
return OK;
}
auto a = p;
const bool pdec = (*a++ == '-' && *a == '(');
const auto pdec = (*a++ == '-' && *a == '(');
if (pdec)
p = a;
if (p.expect('(')) {
Expand All @@ -388,7 +388,7 @@ Error AsmMc68000::parseOperand(StrScanner &scan, Operand &op) const {
return op.getError();
if (p.skipSpaces().expect(')')) {
const auto size = parseSize(p.skipSpaces());
bool over16 = overflowInt16(op.val32);
auto over16 = overflowInt16(op.val32);
if (over16) {
// check if it is near the end of address space.
const auto max = 1UL << uint8_t(addressWidth());
Expand Down Expand Up @@ -509,7 +509,7 @@ Error AsmMc68000::encodeImpl(StrScanner &scan, Insn &_insn) const {
insn.setErrorIf(insn.srcOp, ILLEGAL_BIT_NUMBER);
bitno &= 7;
}
if (insn.oprSize() == SZ_QUAD && bitno >= 32) {
if (insn.oprSize() == SZ_LONG && bitno >= 32) {
insn.setErrorIf(insn.srcOp, ILLEGAL_BIT_NUMBER);
bitno &= 0x1F;
}
Expand Down
22 changes: 10 additions & 12 deletions src/dis_mc68000.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ void DisMc68000::decodeImmediateData(DisInsn &insn, StrBuffer &out, OprSize size
out.letter('#');
uint32_t val;
uint8_t bits;
if (size == SZ_QUAD) {
if (size == SZ_LONG) {
val = insn.readUint32();
bits = 32;
} else {
Expand Down Expand Up @@ -99,7 +99,7 @@ void DisMc68000::decodeEffectiveAddr(DisInsn &insn, StrBuffer &out, const EaMc68
const auto base = (mode == M_INDX) ? ea.reg : REG_PC;
BriefExt ext;
ext.word = insn.readUint16();
const uint8_t val8 = ext.disp();
const auto val8 = ext.disp();
out.letter('(');
if (mode == M_PCIDX) {
const Config::uintptr_t target =
Expand All @@ -117,7 +117,7 @@ void DisMc68000::decodeEffectiveAddr(DisInsn &insn, StrBuffer &out, const EaMc68
if (mode == M_AWORD)
outOprSize(out, SZ_WORD);
if (mode == M_ALONG)
outOprSize(out, SZ_QUAD);
outOprSize(out, SZ_LONG);
if (mode == M_PINC)
out.letter('+');
}
Expand Down Expand Up @@ -156,7 +156,7 @@ StrBuffer &outMoveMltRegList(StrBuffer &out, uint16_t list, bool push) {
int8_t start = -1;
int8_t last = 0;
uint16_t mask = push ? 0x8000 : 0x0001;
for (int8_t i = 0; i < 16; i++) {
for (auto i = 0; i < 16; i++) {
if (list & mask) {
if (start < 0) {
start = last = i;
Expand Down Expand Up @@ -225,7 +225,7 @@ void DisMc68000::decodeOperand(DisInsn &insn, StrBuffer &out, AddrMode mode, uin
insn.setErrorIf(out, ILLEGAL_BIT_NUMBER);
} else if (s == SZ_WORD && opr16 >= 16) {
insn.setErrorIf(out, ILLEGAL_BIT_NUMBER);
} else if (s == SZ_QUAD && opr16 >= 32) {
} else if (s == SZ_LONG && opr16 >= 32) {
insn.setErrorIf(out, ILLEGAL_BIT_NUMBER);
}
outDec(out, opr16, 16);
Expand Down Expand Up @@ -304,18 +304,16 @@ OprSize sizeVal(const DisInsn &insn) {
switch ((opc >> 6) & 3) {
case 0:
return SZ_BYTE;
case 1:
return SZ_WORD;
case 2:
return SZ_QUAD;
return SZ_LONG;
default:
return SZ_OCTA;
return SZ_WORD;
}
}
if (size == SZ_ADDR)
return (opc & (1 << 6)) ? SZ_QUAD : SZ_WORD;
return (opc & (1 << 6)) ? SZ_LONG : SZ_WORD;
if (size == SZ_ADR8)
return (opc & (1 << 8)) ? SZ_QUAD : SZ_WORD;
return (opc & (1 << 8)) ? SZ_LONG : SZ_WORD;
return size;
}

Expand All @@ -331,7 +329,7 @@ Error DisMc68000::decodeImpl(DisMemory &memory, Insn &_insn, StrBuffer &out) con

const auto size = sizeVal(insn);
const auto insnSize = insn.insnSize();
const auto oprSize = (insnSize == ISZ_DATA || insn.hasSize()) ? size : OprSize(insnSize);
const auto oprSize = (insnSize == ISZ_DATA || insnSize == ISZ_FIXD) ? size : OprSize(insnSize);
const auto suffix = sizeSuffix(oprSize);
if (suffix) {
auto save{out};
Expand Down
23 changes: 10 additions & 13 deletions src/entry_mc68000.h
Original file line number Diff line number Diff line change
Expand Up @@ -27,10 +27,9 @@ namespace mc68000 {

enum OprSize : uint8_t {
SZ_NONE = Size::SZ_NONE,
SZ_BYTE = Size::SZ_BYTE,
SZ_WORD = Size::SZ_WORD,
SZ_QUAD = Size::SZ_QUAD,
SZ_OCTA = Size::SZ_OCTA,
SZ_BYTE = Size::SZ_BYTE, // Byte (8 bits)
SZ_WORD = Size::SZ_WORD, // Word (16 bits/2 bytes)
SZ_LONG = Size::SZ_QUAD, // Long (32 bits/4 bytes)
SZ_DATA = Size::SZ_DATA, // _ss|___|___ BYTE=0/WORD=1/LONG=2
SZ_ADDR = Size::SZ_ADDR, // __s|___|___ WORD=0/LONG=1
SZ_ADR8 = 7, // s__|___|___ WORD=0/LONG=1
Expand All @@ -40,7 +39,8 @@ enum InsnSize : uint8_t {
ISZ_NONE = Size::SZ_NONE,
ISZ_BYTE = Size::SZ_BYTE, // .B
ISZ_WORD = Size::SZ_WORD, // .W
ISZ_QUAD = Size::SZ_QUAD, // .L
ISZ_LONG = Size::SZ_QUAD, // .L
ISZ_FIXD = Size::SZ_OCTA, // Fixed size
ISZ_DATA = Size::SZ_DATA,
ISZ_ERROR = 7,
};
Expand Down Expand Up @@ -102,9 +102,9 @@ struct Entry final : entry::Base<Config::opcode_t> {
uint8_t _size;

static constexpr Flags create(AddrMode src, AddrMode dst, OprPos srcPos, OprPos dstPos,
OprSize oSize, InsnSize iSize, bool hasSize) {
OprSize oSize, InsnSize iSize) {
return Flags{static_cast<uint8_t>(src), static_cast<uint8_t>(dst),
Entry::_pos(srcPos, dstPos), Entry::_size(oSize, iSize, hasSize)};
Entry::_pos(srcPos, dstPos), Entry::_size(oSize, iSize)};
}

Flags read() const {
Expand All @@ -117,13 +117,12 @@ struct Entry final : entry::Base<Config::opcode_t> {
OprPos dstPos() const { return OprPos((_pos >> dstPos_gp) & pos_gm); }
OprSize oprSize() const { return OprSize((_size >> oprSize_gp) & size_gm); }
InsnSize insnSize() const { return InsnSize((_size >> insnSize_gp) & size_gm); }
bool hasSize() const { return _size & hasSize_bm; }

void setAddrMode(AddrMode src, AddrMode dst) {
_src = static_cast<uint8_t>(src);
_dst = static_cast<uint8_t>(dst);
}
void setInsnSize(InsnSize size) { _size = Entry::_size(oprSize(), size, hasSize()); }
void setInsnSize(InsnSize size) { _size = Entry::_size(oprSize(), size); }
};

constexpr Entry(Config::opcode_t opCode, Flags flags, const char *name)
Expand All @@ -138,9 +137,9 @@ struct Entry final : entry::Base<Config::opcode_t> {
return (static_cast<uint8_t>(src) << srcPos_gp) | (static_cast<uint8_t>(dst) << dstPos_gp);
}

static constexpr uint8_t _size(OprSize opr, InsnSize insn, bool hasSize) {
static constexpr uint8_t _size(OprSize opr, InsnSize insn) {
return (static_cast<uint8_t>(opr) << oprSize_gp) |
(static_cast<uint8_t>(insn) << insnSize_gp) | (hasSize ? hasSize_bm : 0);
(static_cast<uint8_t>(insn) << insnSize_gp);
}

// |pos|
Expand All @@ -150,9 +149,7 @@ struct Entry final : entry::Base<Config::opcode_t> {
// |size|
static constexpr int oprSize_gp = 0;
static constexpr int insnSize_gp = 3;
static constexpr int hasSize_bp = 6;
static constexpr uint8_t size_gm = 0x07;
static constexpr uint8_t hasSize_bm = (1 << hasSize_bp);
};

} // namespace mc68000
Expand Down
1 change: 0 additions & 1 deletion src/insn_mc68000.h
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,6 @@ struct EntryInsn : EntryInsnBase<Config, Entry> {
OprPos dstPos() const { return flags().dstPos(); }
OprSize oprSize() const { return flags().oprSize(); }
InsnSize insnSize() const { return flags().insnSize(); }
bool hasSize() const { return flags().hasSize(); }
};

struct AsmInsn;
Expand Down
8 changes: 4 additions & 4 deletions src/reg_mc68000.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -111,7 +111,7 @@ InsnSize parseSize(StrScanner &scan) {
} else if (p.iexpect('W')) {
size = ISZ_WORD;
} else if (p.iexpect('L')) {
size = ISZ_QUAD;
size = ISZ_LONG;
}
if (size == ISZ_ERROR || isIdLetter(*p))
return ISZ_ERROR;
Expand All @@ -122,7 +122,7 @@ InsnSize parseSize(StrScanner &scan) {
}

uint8_t sizeNameLen(OprSize size) {
return size == SZ_NONE || size == SZ_OCTA ? 0 : 2;
return size == SZ_NONE ? 0 : 2;
}

char sizeSuffix(OprSize size) {
Expand All @@ -132,7 +132,7 @@ char sizeSuffix(OprSize size) {
case SZ_WORD:
return 'W';
break;
case SZ_QUAD:
case SZ_LONG:
return 'L';
default:
return 0;
Expand Down Expand Up @@ -166,7 +166,7 @@ EaMc68000::EaMc68000(OprSize size_, uint8_t raw_mode, uint8_t regno) {
}

OprSize BriefExt::indexSize() const {
return (word & 0x800) ? SZ_QUAD : SZ_WORD;
return (word & 0x800) ? SZ_LONG : SZ_WORD;
}

RegName BriefExt::index() const {
Expand Down
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