Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.

Mini-Box DCDC-USB, Intelligent buck-boost DC-DC converter with USB interface

Verilog RTL Design

Python library for BusPirate

Bedrock Server manager with backup functionality, plugin support and more.

Command-line program to download videos from YouTube.com and other video sites

Script to remove Windows 10 bloatware.

Creates a .SVG symbol from a VHDL entity. Colors and some other properties can be adjusted.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

papyrus.js renders maps of Minecraft: Bedrock Edition worlds using node.js, LevelDB and leaflet.

PapyrusCS renders maps of Minecraft: Bedrock Edition worlds using C#, LevelDB and leaflet.

The main repository for the Linux and Mac OS Bedrock edition Minecraft launcher.

🌊 Digital timing diagram rendering engine

CLI for WaveDrom

Please note this is a legacy repository, please go to: https://github.com/minecraft-linux/mcpelauncher-manifest/wiki

A Python framework for creating, editing, and invoking Noisy Intermediate-Scale Quantum (NISQ) circuits.

FPGA VHDL project for using the NHD-2.4-240320CF TFT display (ST7789S driver IC and 16 bit parallel interface) with an Arty Z7-20 board

Verilog Ethernet components for FPGA implementation

EPICS IOC for Tektronix scopes

this tries to be a minimal cmake example, that covers sources resources dependencies and packaging.