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rejunity · Mar 18, 2024 · 481142d · 481142d
1 parent d6550de
commit 481142d
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/1_58bit_mul.v b/src/1_58bit_mul.v
@@ -88,7 +88,7 @@ module systolic_array (
 
     output wire [7:0] out
 );
-    localparam SLICES = 3;
+    localparam SLICES = 1;
     localparam SLICE_BITS = $clog2(SLICES);
     localparam SLICES_MINUS_1 = SLICES - 1;
     localparam W = 1 * SLICES;

diff --git a/test/test.py b/test/test.py
@@ -9,7 +9,7 @@
 
 # PACK_5_WEIGHTS = False
 PACK_5_WEIGHTS = True
-COMPUTE_SLICES = 3
+COMPUTE_SLICES = 1
 
 WEIGHTS_PER_BYTE     = 5 if PACK_5_WEIGHTS else 4
 COMPUTE_BLOCK_WIDTH  = 1               *COMPUTE_SLICES