Integrated Circuits Lab @ DUTH

All

14 repositories

DRIM
Public
DUTH RISC-V Microprocessor
processor architecture systemverilog risc-v riscv32
SystemVerilog
•
MIT License
•7•19•0•0•Updated Dec 4, 2024Dec 4, 2024
SIMD-Softmax
Public
C++
•
MIT License
•0•0•0•0•Updated Nov 6, 2024Nov 6, 2024
DRIM-S
Public
DUTH RISC-V Superscalar Microprocessor
processor riscv systemverilog superscalar risc-v
SystemVerilog
•
MIT License
•10•30•0•0•Updated Oct 23, 2024Oct 23, 2024
online-fp-add
Public
C++
•
MIT License
•0•0•0•0•Updated Oct 7, 2024Oct 7, 2024
MLMB4HLS
Public
C++
•
MIT License
•0•1•0•0•Updated Dec 13, 2023Dec 13, 2023
Data-Clustering-HLS-Lib
Public
A C++ library of data clustering algorithms for High-Level Synthesis
C++
•
MIT License
•0•1•0•0•Updated Nov 30, 2023Nov 30, 2023
ApproximatePrefix
Public
Synthesis of Approximate Parallel Prefix Adders
C++
•
MIT License
•1•0•1•0•Updated Jul 3, 2023Jul 3, 2023
DRIM4HLS
Public
DUTH RISC V Microprocessor for High Level Synthesis
systemc risc-v high-level-synthesis risc-processor
C++
•
Apache License 2.0
•2•10•0•0•Updated Jun 23, 2023Jun 23, 2023
CompArchCourseDUTH
Public
Material related to the Computer Architecture course at ECE, DUTH
SystemVerilog
•1•0•0•0•Updated Mar 5, 2023Mar 5, 2023
Fast-Float4HLS
Public
Fast Floating Point Operators for High Level Synthesis
low-power high-level-synthesis floating-point-arithmetic fused-dot-product
C++
•
MIT License
•4•20•0•0•Updated Feb 23, 2023Feb 23, 2023
FusedGCN4HLS
Public
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
machine-learning graph-convolutional-networks high-level-synthesis systolic-arrays three-matrix-multiplication
C++
•
MIT License
•2•22•0•0•Updated Jul 29, 2022Jul 29, 2022
NoCpad
Public
HLS for Networks-on-Chip
high-level-synthesis network-on-chip cache-coherence axi4-lite hls noc axi4
C++
•
Other
•5•33•1•0•Updated Feb 18, 2021Feb 18, 2021
RISC-V-Vector
Public
Vector processor for RISC-V vector ISA
riscv systemverilog risc-v vector-processor
SystemVerilog
•
Other
•25•113•0•0•Updated Oct 19, 2020Oct 19, 2020
shared-buffer-hw
Public
A multi-queue buffer with dynamic buffer space allocation and its Formal Verification TB
SystemVerilog
•
Other
•4•2•0•0•Updated Nov 6, 2018Nov 6, 2018