Repositories list

• SpinalHDL

  Public
  Scala based HDL

  fpgartlscala+ 2vhdlverilog

  Scala

  •

  Other

  •338•1.7k•128•28•Updated Feb 14, 2025Feb 14, 2025

• VexRiscv

  Public
  A FPGA friendly 32 bit RISC-V CPU implementation

  fpgavhdlriscv+ 5verilogspinalhdlsoftcorecpusoc

  Assembly

  •

  MIT License

  •426•2.7k•107•5•Updated Feb 14, 2025Feb 14, 2025

• VexiiRiscv

  Public
  Like VexRiscv, but, Harder, Better, Faster, Stronger

  Scala

  •

  MIT License

  •14•142•3•0•Updated Feb 13, 2025Feb 13, 2025

• SpinalDoc-RTD

  Public
  The sources of the online SpinalHDL doc

  documentationspinalhdl

  Python

  •

  Creative Commons Zero v1.0 Universal

  •61•26•21•6•Updated Feb 12, 2025Feb 12, 2025

• SpinalTemplateSbtDependencies

  Public
  An SpinalHDL project example which use VexRiscv git as a dependency

  Scala

  •2•5•0•0•Updated Feb 12, 2025Feb 12, 2025

• NaxRiscv

  Public
  Scala

  •

  MIT License

  •40•275•42•0•Updated Feb 12, 2025Feb 12, 2025

• VexiiRiscv-RTD

  Public
  Python

  •

  Creative Commons Zero v1.0 Universal

  •3•1•0•1•Updated Feb 10, 2025Feb 10, 2025

• rvls

  Public
  RISCV lock-step checker based on Spike

  C++

  •2•10•0•0•Updated Jan 30, 2025Jan 30, 2025

• riscv-isa-sim

  Public
  Spike, a RISC-V ISA Simulator

  C

  •

  Other

  •900•1•0•2•Updated Jan 30, 2025Jan 30, 2025

• NaxSoftware

  Public
  C

  •5•9•0•0•Updated Jan 30, 2025Jan 30, 2025

• VexiiFirmware

  Public
  C

  •0•1•0•0•Updated Jan 6, 2025Jan 6, 2025

• SpinalTemplateSbt

  Public template
  A basic SpinalHDL project

  Scala

  •65•80•5•5•Updated Dec 17, 2024Dec 17, 2024

• SpinalDoc

  Public
  SpinalHDL documentation assets (pictures, slides, ...)

  HTML

  •13•32•0•0•Updated Dec 10, 2024Dec 10, 2024

• SpinalSchemaGen

  Public
  Scala

  •1•4•0•0•Updated Nov 22, 2024Nov 22, 2024

• docker

  Public
  Dockerfile

  •7•4•0•1•Updated Oct 15, 2024Oct 15, 2024

• SpinalCrypto

  Public
  SpinalHDL - Cryptography libraries

  cryptographyscalacrypto+ 11fpgaaesvhdlmd5shartlverilog+ 4

  Scala

  •

  MIT License

  •19•51•3•0•Updated Jul 19, 2024Jul 19, 2024

• SpinalWorkshop

  Public
  Labs to learn SpinalHDL

  Scala

  •40•146•7•0•Updated Jul 4, 2024Jul 4, 2024

• Spinal-bootcamp

  Public
  SpinalHDL-tutorial based on Jupyter Notebook

  Jupyter Notebook

  •48•44•0•0•Updated Apr 9, 2024Apr 9, 2024

• SaxonSoc

  Public
  SoC based on VexRiscv and ICE40 UP5K

  riscvrtlsoc

  Scala

  •

  MIT License

  •41•152•15•0•Updated Apr 4, 2024Apr 4, 2024

• openocd_riscv

  Public
  Spen's Official OpenOCD Mirror

  C

  •

  Other

  •817•48•10•0•Updated Mar 5, 2024Mar 5, 2024

• NaxRiscv-Rtd

  Public
  Python

  •3•2•0•0•Updated Feb 15, 2024Feb 15, 2024

• naxriscv_doc

  Public
  MIT License

  •4•0•0•0•Updated Dec 19, 2023Dec 19, 2023

• embench-iot

  Public
  The main Embench repository

  C

  •

  GNU General Public License v3.0

  •109•0•0•0•Updated Dec 1, 2023Dec 1, 2023

• SpinalTemplateGradle

  Public
  A basic SpinalHDL project, configured with Gradle instead of SBT

  spinalhdl

  Scala

  •3•4•1•1•Updated Jul 5, 2023Jul 5, 2023

• CocotbLib

  Public
  Python

  •

  MIT License

  •7•15•1•21•Updated May 17, 2023May 17, 2023

• buildroot-spinal-saxon

  Public
  C

  •6•1•0•0•Updated Oct 3, 2022Oct 3, 2022

• linux

  Public
  C

  •

  Other

  •1•0•0•0•Updated Sep 5, 2022Sep 5, 2022

• riscv-compliance

  Public
  Assembly

  •

  BSD 3-Clause "New" or "Revised" License

  •218•0•0•0•Updated Mar 15, 2022Mar 15, 2022

• coremark

  Public
  CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

  C

  •

  Other

  •340•0•0•0•Updated Dec 22, 2021Dec 22, 2021

• VexRiscvSocSoftware

  Public
  C

  •16•26•0•0•Updated Dec 15, 2021Dec 15, 2021