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Altera apu agilex7 #2647

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merged 23 commits into from
Dec 4, 2024
Merged

Altera apu agilex7 #2647

merged 23 commits into from
Dec 4, 2024

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AngelaGonzalezMarino
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@AngelaGonzalezMarino AngelaGonzalezMarino commented Dec 3, 2024 •
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This PR is adding the APU design adapted to Altera Agilex7 FPGA.

Submodules to use PULP GPIO in APU instead of Xilinx GPIO IP
AXI data width adapter (open source)
adaptation of debug module to use with vJTAG IP (from Thales AVS)
Top level of cva6 APU + cva6 peripherals adapted to Altera

It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.

AngelaGonzalezMarino and others added 18 commits November 27, 2024 13:07
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github-actions bot commented Dec 3, 2024

✔️ successful run, report available here.

JeanRochCoulon
JeanRochCoulon reviewed Dec 4, 2024
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@AngelaGonzalezMarino AngelaGonzalezMarino mentioned this pull request Dec 4, 2024
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github-actions bot commented Dec 4, 2024

✔️ successful run, report available here.

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github-actions bot commented Dec 4, 2024

✔️ successful run, report available here.

JeanRochCoulon
JeanRochCoulon reviewed Dec 4, 2024
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github-actions bot commented Dec 4, 2024

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github-actions bot commented Dec 4, 2024

✔️ successful run, report available here.

@JeanRochCoulon JeanRochCoulon merged commit f7eb9c1 into openhwgroup:master Dec 4, 2024
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@AngelaGonzalezMarino
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thanks!

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@JeanRochCoulon JeanRochCoulon JeanRochCoulon left review comments

@zarubaf zarubaf Awaiting requested review from zarubaf zarubaf is a code owner

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@AngelaGonzalezMarino @JeanRochCoulon