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[BUG] [CV32A65X] Writes into PMPADDR registers do not follow specification #2657

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zchamski opened this issue Dec 9, 2024 · 2 comments
Open
1 task done

[BUG] [CV32A65X] Writes into PMPADDR registers do not follow specification #2657

zchamski opened this issue Dec 9, 2024 · 2 comments
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notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system

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zchamski commented Dec 9, 2024

Is there an existing CVA6 bug for this?

  • I have searched the existing bug issues

Bug Description

Since the CV32A65X specification has been updated to make bit 0 of pmpaddrN registers read-only zero (see #2651), the implementation of pmpaddrN CSR writes is not in line with the spec. The incriminated code is https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L1710C1-L1713C71.
@zchamski zchamski added the Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system label Dec 9, 2024
JeanRochCoulon added a commit that referenced this issue Dec 9, 2024
@JeanRochCoulon
fix #2657
e1eebe8 
set bit0 of PMPADDR as read only zero
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Fixed by #2658

This was referenced Dec 18, 2024
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@JeanRochCoulon JeanRochCoulon added the CV32A65X Part: Embedded configuration label Jan 2, 2025
ASintzoff pushed a commit that referenced this issue Jan 7, 2025
@JeanRochCoulon
Fix #2665 #2400 #2657 (#2685)
2155d0e 
* Fix #2400: define new PmpNapotEn parameter to disable NAPOT

* Fix #2665 by removing NA4 related RTL lines

* Fix Spyglass

* Fix gate count
@AyoubJalali AyoubJalali mentioned this issue Jan 7, 2025
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JeanRochCoulon commented Jan 7, 2025 •
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This GitHub issue has not been fixed by #2685. As 60x and 65x will not supported PMP, I removed the CV32A65X label.

@JeanRochCoulon JeanRochCoulon added notCV32A65X It is not an CV32A65X issue and removed CV32A65X Part: Embedded configuration labels Jan 7, 2025
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notCV32A65X It is not an CV32A65X issue Type:Bug For bugs in the RTL, Documentation, Verification environment or Tool and Build system
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fix pmpaddr ThalesSiliconSecurity/cva6
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@JeanRochCoulon @zchamski