Merge branch 'master' into hyp/script

core/cache_subsystem/wt_axi_adapter.sv

@@ -64,6 +64,7 @@ module wt_axi_adapter
   localparam MaxNumWords = $clog2(CVA6Cfg.AxiDataWidth / 8);
   localparam AxiRdBlenIcache = CVA6Cfg.ICACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
   localparam AxiRdBlenDcache = CVA6Cfg.DCACHE_LINE_WIDTH / CVA6Cfg.AxiDataWidth - 1;
+  localparam AxiBlenWidth = AxiNumWords > 1 ? $clog2(AxiNumWords) : AxiNumWords;
 
   ///////////////////////////////////////////////////////
   // request path
@@ -82,7 +83,7 @@ module wt_axi_adapter
   logic axi_wr_valid, axi_rd_valid, axi_rd_rdy, axi_wr_rdy;
   logic axi_rd_lock, axi_wr_lock, axi_rd_exokay, axi_wr_exokay, wr_exokay;
   logic [CVA6Cfg.AxiAddrWidth-1:0] axi_rd_addr, axi_wr_addr;
-  logic [$clog2(AxiNumWords)-1:0] axi_rd_blen, axi_wr_blen;
+  logic [AxiBlenWidth-1:0] axi_rd_blen, axi_wr_blen;
   logic [2:0] axi_rd_size, axi_wr_size;
   logic [CVA6Cfg.AxiIdWidth-1:0]
       axi_rd_id_in, axi_wr_id_in, axi_rd_id_out, axi_wr_id_out, wr_id_out;
@@ -170,14 +171,14 @@ module wt_axi_adapter
       // If dcache_data.size MSB is set, we want to read as much as possible
       axi_rd_size = dcache_data.size[2] ? MaxNumWords[2:0] : dcache_data.size;
       if (dcache_data.size[2]) begin
-        axi_rd_blen = AxiRdBlenDcache[$clog2(AxiNumWords)-1:0];
+        axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
       end
     end else begin
       // Cast to AXI address width
       axi_rd_addr = {{CVA6Cfg.AxiAddrWidth - CVA6Cfg.PLEN{1'b0}}, icache_data.paddr};
       axi_rd_size = MaxNumWords[2:0];  // always request max number of words in case of ifill
       if (!icache_data.nc) begin
-        axi_rd_blen = AxiRdBlenIcache[$clog2(AxiNumWords)-1:0];
+        axi_rd_blen = AxiRdBlenDcache[AxiBlenWidth-1:0];
       end
     end
 

docs/design/design-manual/source/cva6_frontend.adoc

@@ -256,7 +256,7 @@ DECODE pops them when decode stage is ready and indicates to the FRONTEND the in
 
 
 The instruction queue contains two FIFOs: one for instructions and one for addresses, which stores addresses in case of a prediction.
-The instruction FIFO can hold up to 4×{INSTR_PER_FETCH} instructions, while the address FIFO can hold up to 2 addresses.
+The instruction FIFO can hold up to 4×{instr-per-fetch} instructions, while the address FIFO can hold up to 2 addresses.
 If the instruction FIFO is full, a replay request is sent to inform the fetch mechanism to replay the fetch.
 If the address FIFO is full and there is a prediction, a replay request is sent to inform the fetch mechanism to replay the fetch, even if the instruction FIFO is not full.
 
@@ -285,23 +285,23 @@ BHT (Branch History Table) submodule
 The BHT is implemented as a memory which is composed of {BHTEntries} entries.
 The BHT is a two-dimensional table:
 
-*	The first dimension represents the access address, with a length equal to `{BHTEntries} / {INSTR_PER_FETCH}`.
-*	The second dimension represents the row index, with a length equal to `INSTR_PER_FETCH`.
+*	The first dimension represents the access address, with a length equal to `{BHTEntries} / {instr-per-fetch}`.
+*	The second dimension represents the row index, with a length equal to `{instr-per-fetch}`.
 
 In the case of branch prediction, the BHT uses only part of the virtual address to get the value of the saturation counter.
 In the case of a valid misprediction, the BHT uses only part of the misprediction address to access the BHT table and update the saturation counter.
 
-'UPPER_ADDRESS_INDEX = $clog2(BHTDepth) + ((RVC == 1) ? 1 : 2)'
+`UPPER_ADDRESS_INDEX = $clog2(BHTDepth) + ((RVC == 1) ? 1 : 2)`
 
-'LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)'
+`LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 + $clog2(INSTR_PER_FETCH)`
 
 `ACCESS_ADDRESS = PC/MISPREDICT_ADDRESS [ UPPER_ADDRESS_INDEX : LOWER_ADDRESS_INDEX ]`
 
 The lower address bits of the virtual address point to the memory entry.
 
-'UPPER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 +  $clog2(INSTR_PER_FETCH)'
+`UPPER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 +  $clog2(INSTR_PER_FETCH)`
 
-'LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 +    $clog2(INSTR_PER_FETCH)'
+`LOWER_ADDRESS_INDEX = (RVC == 1) ? 1 : 2 +    $clog2(INSTR_PER_FETCH)`
 
 `ACCESS_INDEX = PC/MISPREDICT_ADDRESS [ UPPER_ADDRESS_INDEX : LOWER_ADDRESS_INDEX]`