Update version of the HPDcache submodule (#1673)

openhwgroup · Dec 6, 2023 · 2cfa4e5 · 2cfa4e5
1 parent 9952bce
commit 2cfa4e5
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Showing 5 changed files with 11 additions and 3 deletions.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -35,7 +35,7 @@ jobs:
     strategy:
       matrix:
         testcase: [asm-tests, mul, amo, fp, benchmarks]
-        target: [cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb]
+        target: [cv64a6_imafdc_sv39, cv64a6_imafdc_sv39_wb, cv64a6_imafdc_sv39_hpdcache]
     env:
       RISCV: /riscv
     needs:

diff --git a/core/Flist.cva6 b/core/Flist.cva6
@@ -157,6 +157,11 @@ ${CVA6_REPO_DIR}/core/cache_subsystem/std_cache_subsystem.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/std_nbdcache.sv
 ${HPDCACHE_TARGET_CFG}
 -F ${HPDCACHE_DIR}/rtl/hpdcache.Flist
+${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv
+${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv
+${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_resp_demux.sv
+${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_read.sv
+${HPDCACHE_DIR}/rtl/src/utils/hpdcache_mem_to_axi_write.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv
 ${CVA6_REPO_DIR}/core/cache_subsystem/cva6_hpdcache_if_adapter.sv

diff --git a/core/cache_subsystem/hpdcache b/core/cache_subsystem/hpdcache
diff --git a/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv b/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
@@ -144,6 +144,7 @@ package cva6_config_pkg;
       ),
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),
+      MaxOutstandingStores: unsigned'(7),
       DebugEn: bit'(1),
       NonIdemPotenceEn: bit'(0),
       AxiBurstWriteEn: bit'(0)

diff --git a/core/include/cva6_hpdcache_default_config_pkg.sv b/core/include/cva6_hpdcache_default_config_pkg.sv
@@ -85,7 +85,7 @@ package hpdcache_params_pkg;
   localparam int unsigned PARAM_MSHR_WAYS = (CVA6ConfigNrLoadBufEntries > 4) ? 4 : 2;
 
   //  HPDcache MSHR number of ways in the same SRAM word
-  localparam int unsigned PARAM_MSHR_WAYS_PER_RAM_WORD = PARAM_MSHR_WAYS > 1 ? 2 : 1;
+  localparam int unsigned PARAM_MSHR_WAYS_PER_RAM_WORD = (PARAM_MSHR_WAYS > 1) ? 2 : 1;
 
   //  HPDcache MSHR number of sets in the same SRAM
   localparam int unsigned PARAM_MSHR_SETS_PER_RAM = PARAM_MSHR_SETS;
@@ -97,6 +97,7 @@ package hpdcache_params_pkg;
 
   //  HPDcache MSHR whether uses FFs or SRAM
   localparam bit PARAM_MSHR_USE_REGBANK = (PARAM_MSHR_SETS * PARAM_MSHR_WAYS) <= 16;
+  localparam bit PARAM_REFILL_CORE_RSP_FEEDTHROUGH = 1'b1;
   //  }}}
 
   //  Definition of constants and types for the Write Buffer (WBUF)
@@ -112,6 +113,7 @@ package hpdcache_params_pkg;
 
   //  HPDcache Write-Buffer threshold counter width (in bits)
   localparam int unsigned PARAM_WBUF_TIMECNT_WIDTH = 3;
+  localparam bit PARAM_WBUF_SEND_FEEDTHROUGH = 1'b0;
   //  }}}
 
   //  Definition of constants and types for the Replay Table (RTAB)
+1 −5		rtl/hpdcache.Flist
+107 −84		rtl/src/common/hpdcache_fifo_reg.sv
+1 −1		rtl/src/common/hpdcache_fxarb.sv
+2 −2		rtl/src/common/hpdcache_rrarb.sv
+89 −0		rtl/src/common/hpdcache_sync_buffer.sv
+2 −2		rtl/src/hpdcache_cmo.sv
+1 −1		rtl/src/hpdcache_ctrl.sv
+2 −2		rtl/src/hpdcache_memctrl.sv
+40 −54		rtl/src/hpdcache_miss_handler.sv
+10 −0		rtl/src/hpdcache_pkg.sv
+10 −10		rtl/src/hpdcache_rtab.sv
+5 −5		rtl/src/hpdcache_uncached.sv
+30 −37		rtl/src/hpdcache_wbuf.sv
+2 −1		rtl/src/hpdcache_wbuf_wrapper.sv
+1 −1		rtl/src/target/cva6/cva6_hpdcache_if_adapter.sv
+25 −3		rtl/src/target/generic/hpdcache_params_pkg.sv