Merge branch 'master' into nopmp

Makefile

@@ -40,7 +40,10 @@ torture-logs   :=
 elf_file        ?= tmp/riscv-tests/build/benchmarks/dhrystone.riscv
 # board name for bitstream generation. Currently supported: kc705, genesys2, nexys_video
 BOARD          ?= genesys2
-
+ALTERA_BOARD		 ?= DK-DEV-AGF014E3ES
+ALTERA_FAMILY	 ?= "AGILEX"
+ALTERA_PART		 ?= AGFB014R24B2E2V
+PLATFORM			 = "PLAT_XILINX"
 # root path
 mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
 root-dir := $(dir $(mkfile_path))
@@ -166,17 +169,11 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         $(wildcard corev_apu/fpga/src/axi_slice/src/*.sv)                            \
         $(wildcard corev_apu/src/axi_riscv_atomics/src/*.sv)                         \
         $(wildcard corev_apu/axi_mem_if/src/*.sv)                                    \
+				$(wildcard corev_apu/riscv-dbg/src/*.sv)                                   \
         corev_apu/rv_plic/rtl/rv_plic_target.sv                                      \
         corev_apu/rv_plic/rtl/rv_plic_gateway.sv                                     \
         corev_apu/rv_plic/rtl/plic_regmap.sv                                         \
         corev_apu/rv_plic/rtl/plic_top.sv                                            \
-        corev_apu/riscv-dbg/src/dmi_cdc.sv                                           \
-        corev_apu/riscv-dbg/src/dmi_jtag.sv                                          \
-        corev_apu/riscv-dbg/src/dmi_jtag_tap.sv                                      \
-        corev_apu/riscv-dbg/src/dm_csrs.sv                                           \
-        corev_apu/riscv-dbg/src/dm_mem.sv                                            \
-        corev_apu/riscv-dbg/src/dm_sba.sv                                            \
-        corev_apu/riscv-dbg/src/dm_top.sv                                            \
         corev_apu/riscv-dbg/debug_rom/debug_rom.sv                                   \
         corev_apu/register_interface/src/apb_to_reg.sv                               \
         vendor/pulp-platform/axi/src/axi_multicut.sv                                 \
@@ -236,6 +233,52 @@ uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv     \
 uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv))
 
 fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/util/hpdcache_sram_1rw.sv common/local/util/hpdcache_sram_wbyteenable_1rw.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv
+
+altera_src := $(shell find $(root-dir)/corev_apu/altera/src -type f \( -name "*.v" -o -name "*.sv" -o -name "*.svh" \) -print | sed 's|//|/|g')
+altera_src += $(src)
+altera_src += $(shell find $(root-dir)/corev_apu/fpga/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
+altera_src += $(shell find $(root-dir)core/cvfpu/src/common_cells/src/ -maxdepth 1 -type f \( -name "*.v" -o -name "*.sv" -o -name "*.vhd" -o -name "*.svh" \) -print)
+altera_axi_src := $(shell find $(root-dir)/vendor/pulp-platform/axi/src -type f \( -name "*.v" -o -name "*.sv" \) -print | sed 's|//|/|g')
+
+altera_src += $(root-dir)corev_apu/rv_plic/rtl/top_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/tlul_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_top.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic_reg_pkg.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/rv_plic.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/prim_subreg_ext.sv \
+							$(root-dir)corev_apu/rv_plic/rtl/prim_subreg.sv \
+							$(root-dir)vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv \
+							$(root-dir)riscv-dbg/src/dm_obi_top.sv \
+							$(root-dir)core/include/instr_tracer_pkg.sv \
+							$(root-dir)core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv \
+							$(root-dir)core/cache_subsystem/amo_alu.sv
+
+altera_filter := corev_apu/tb/ariane_testharness.sv \
+								corev_apu/tb/ariane_peripherals.sv \
+								corev_apu/tb/rvfi_tracer.sv \
+								corev_apu/tb/common/uart.sv \
+								corev_apu/tb/common/SimDTM.sv \
+								corev_apu/tb/common/SimJTAG.sv \
+								corev_apu/fpga/src/apb/src/apb_test.sv \
+								corev_apu/fpga/src/ariane_xilinx.sv \
+								corev_apu/fpga/ariane_peripherals_xilinx.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_cdc.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_regs.sv \
+								corev_apu/fpga/src/apb/test/tb_apb_demux.sv \
+								corev_apu/fpga/src/gpio/test/tb_gpio.sv \
+								vendor/pulp-platform/axi/src/axi_test.sv \
+								corev_apu/riscv-dbg/src/dm_pkg.sv \
+								corev_apu/riscv-dbg/src/dmi_jtag_tap.sv \
+								corev_apu/riscv-dbg/src/dmi_jtag.sv \
+								corev_apu/fpga/src/apb_uart/src/reg_uart_wrap.sv
+
+altera_filter := $(addprefix $(root-dir), $(altera_filter))
+xil_debug_filter = $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_obi_top.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dm_pkg.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag_tap.sv)
+xil_debug_filter += $(addprefix $(root-dir), corev_apu/riscv-dbg/src/dmi_vjtag.sv)						
+src := $(filter-out $(xil_debug_filter), $(src))
+
 fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
 
 # look for testbenches
@@ -738,7 +781,7 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co
 fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv)
 
 src/bootrom/bootrom_$(XLEN).sv:
-	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv
+	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv
 
 fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
 	@echo "[FPGA] Generate sources"
@@ -750,6 +793,19 @@ fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
 	@echo "[FPGA] Generate Bitstream"
 	$(MAKE) -C corev_apu/fpga BOARD=$(BOARD) XILINX_PART=$(XILINX_PART) XILINX_BOARD=$(XILINX_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
 
+altera: PLATFORM := "PLAT_AGILEX"
+
+altera: $(ariane_pkg) $(src) $(fpga_src) $(src_flist)
+	@echo "[FPGA] Generate sources"
+	@echo $(ariane_pkg) > corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter), $(src_flist))		>> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter), $(src)) 	   >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(altera_filter), $(fpga_src))		 >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter) $(uart_src_sv), $(altera_src))   >> corev_apu/altera/sourcelist.txt
+	@echo $(filter-out $(fpga_filter) $(altera_filter), $(altera_axi_src))   >> corev_apu/altera/sourcelist.txt
+	@echo "[FPGA] Generate Bitstream"
+	$(MAKE) -C corev_apu/altera ALTERA_PART=$(ALTERA_PART) ALTERA_BOARD=$(ALTERA_BOARD) CLK_PERIOD_NS=$(CLK_PERIOD_NS)
+
 .PHONY: fpga
 
 build-spike:
@@ -762,6 +818,9 @@ clean:
 	$(MAKE) -C corev_apu/fpga clean
 	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) clean
 
+clean-altera: clean
+	$(MAKE) -C corev_apu/altera clean
+
 .PHONY:
 	build sim sim-verilate clean                                              \
 	$(riscv-asm-tests) $(addsuffix _verilator,$(riscv-asm-tests))             \

core/Flist.cva6

@@ -29,6 +29,8 @@
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv
 ${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv
+${CVA6_REPO_DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv
 
 +incdir+${CVA6_REPO_DIR}/core/include/
 +incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/

core/cva6.sv

@@ -1533,9 +1533,7 @@ module cva6
   // Parameter Check
   // -------------------
   // pragma translate_off
-`ifndef VERILATOR
   initial config_pkg::check_cfg(CVA6Cfg);
-`endif
   // pragma translate_on
 
   // -------------------

core/cva6_fifo_v3.sv

@@ -209,7 +209,6 @@ module cva6_fifo_v3 #(
   end
 
   // pragma translate_off
-`ifndef VERILATOR
   initial begin
     assert (DEPTH > 0)
     else $error("DEPTH must be greater than 0.");
@@ -222,7 +221,6 @@ module cva6_fifo_v3 #(
   empty_read :
   assert property (@(posedge clk_i) disable iff (~rst_ni) (empty_o |-> ~pop_i))
   else $fatal(1, "Trying to pop data although the FIFO is empty.");
-`endif
   // pragma translate_on
 
 endmodule  // fifo_v3

core/cva6_mmu/cva6_tlb.sv

@@ -400,7 +400,6 @@ for (
   //--------------
 
   //pragma translate_off
-`ifndef VERILATOR
 
   initial begin : p_assertions
     assert ((TLB_ENTRIES % 2 == 0) && (TLB_ENTRIES > 1))
@@ -435,7 +434,6 @@ for (
     $stop();
   end
 
-`endif
   //pragma translate_on
 
 endmodule

core/frontend/frontend.sv

@@ -575,12 +575,4 @@ module frontend
       .fetch_entry_ready_i(fetch_entry_ready_i)    // to back-end
   );
 
-  // pragma translate_off
-`ifndef VERILATOR
-  initial begin
-    assert (CVA6Cfg.FETCH_WIDTH == 32 || CVA6Cfg.FETCH_WIDTH == 64)
-    else $fatal(1, "[frontend] fetch width != not supported");
-  end
-`endif
-  // pragma translate_on
 endmodule

core/frontend/instr_queue.sv

@@ -551,7 +551,6 @@ module instr_queue
   end
 
   // pragma translate_off
-`ifndef VERILATOR
   replay_address_fifo :
   assert property (@(posedge clk_i) disable iff (!rst_ni) replay_o |-> !i_fifo_address.push_i)
   else $fatal(1, "[instr_queue] Pushing address although replay asserted");
@@ -562,6 +561,5 @@ module instr_queue
     $error("Output select should be one-hot encoded");
     $stop();
   end
-`endif
   // pragma translate_on
 endmodule

core/include/config_pkg.sv

@@ -369,7 +369,6 @@ package config_pkg;
   /// sense for all parameters, here is the place to sanity check them.
   function automatic void check_cfg(cva6_cfg_t Cfg);
     // pragma translate_off
-`ifndef VERILATOR
     assert (Cfg.RASDepth > 0);
     assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries));
     assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries));
@@ -379,7 +378,8 @@ package config_pkg;
     assert (Cfg.NrPMPEntries <= 64);
     assert (!(Cfg.SuperscalarEn && Cfg.RVF));
     assert (!(Cfg.SuperscalarEn && Cfg.RVZCMP));
-`endif
+    assert (Cfg.FETCH_WIDTH == 32 || Cfg.FETCH_WIDTH == 64)
+    else $fatal(1, "[frontend] fetch width != not supported");
     // pragma translate_on
   endfunction
 

core/load_unit.sv

@@ -546,7 +546,6 @@ module load_unit
   ///////////////////////////////////////////////////////
 
   //pragma translate_off
-`ifndef VERILATOR
   initial
     assert (CVA6Cfg.DcacheIdWidth >= REQ_ID_BITS)
     else $fatal(1, "DcacheIdWidth parameter is not wide enough to encode pending loads");
@@ -563,7 +562,6 @@ module load_unit
   assert property (@(posedge clk_i) disable iff (~rst_ni)
         ldbuf_w |->  (ldbuf_wdata.operation inside {ariane_pkg::LB, ariane_pkg::LBU}) |-> ldbuf_wdata.address_offset < 8)
   else $fatal(1, "invalid address offset used with {LB, LBU}");
-`endif
   //pragma translate_on
 
 endmodule