Merge branch 'master' into dev/SEIP

docs/riscv-isa/src/colophon.adoc

@@ -7,7 +7,7 @@
 This document describes the RISC-V unprivileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Document Version 20241017_*
+[.big]*_Preface to Document Version 20241101_*
 
 This document describes the RISC-V unprivileged architecture.
 

docs/riscv-isa/src/machine.adoc

@@ -226,10 +226,17 @@ supervisor modes respectively.
 
 The "X" bit will be set if there are any non-standard extensions.
 
-When "B" bit is 1, the implementation supports the instructions provided by the
-Zba, Zbb, and Zbs extensions. When "B" bit is 0, it indicates that the
+When the "B" bit is 1, the implementation supports the instructions provided by the
+Zba, Zbb, and Zbs extensions. When the "B" bit is 0, it indicates that the
 implementation may not support one or more of the Zba, Zbb, or Zbs extensions.
 
+When the "M" bit is 1, the implementation supports all multiply and
+division instructions defined by the M extension. When the "M" bit
+is 0, it indicates that the implementation may not support those
+instructions. However if the Zmmul extension is supported then
+the multiply instructions it specifies are supported irrespective
+of the value of the "M" bit.
+
 ifeval::[{note} == true]
 [NOTE]
 ====
@@ -1554,7 +1561,7 @@ additional microarchitectural bits might be maintained in the extension
 to further reduce context save and restore overhead.
 
 The SD bit is read-only and is set when either the FS, VS, or XS bits
-encode a Dirty state (i.e., SD=((FS==11) OR (XS==11) OR (VS==11))). This
+encode a Dirty state (i.e., `SD=(FS==0b11 OR XS==0b11 OR VS==0b11)`). This
 allows privileged code to quickly determine when no additional context
 save is required beyond the integer register set and `pc`.
 
@@ -3865,7 +3872,9 @@ and I/O regions may be accessed with either _relaxed_ or _strong_
 ordering. Accesses to an I/O region with relaxed ordering are generally
 observed by other harts and bus mastering devices in a manner similar to
 the ordering of accesses to an RVWMO memory region, as discussed in
-Section A.4.2 in Volume I of this specification. By contrast, accesses
+the I/O Ordering section in the RVWMO Explanatory Material appendix
+of Volume I of this specification.
+By contrast, accesses
 to an I/O region with strong ordering are generally observed by other
 harts and bus mastering devices in program order.
 

docs/riscv-isa/src/priv-preface.adoc

@@ -6,6 +6,98 @@
 This document describes the RISC-V privileged architecture tailored for
 OpenHW Group {ohg-config}.
 
+[.big]*_Preface to Version 20241101_*
+
+This document describes the RISC-V privileged architecture. This
+release, version 20241101, contains the following versions of the RISC-V ISA
+modules:
+
+[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
+|===
+|Module |Version |Status
+|_Machine ISA_ +
+*Smstateen Extension* +
+*Smcsrind/Sscsrind Extension* +
+*Smepmp Extension* +
+*Smcntrpmf Extension* +
+*Smrnmi Extension* +
+*Smcdeleg Extension* +
+*Smdbltrp Extension* +
+_Supervisor ISA_ +
+*Svade Extension* +
+*Svnapot Extension* +
+*Svpbmt Extension* +
+*Svinval Extension* +
+*Svadu Extension* +
+*Sstc Extension* +
+*Sscofpmf Extension* +
+*Ssdbltrp Extension* +
+*Ssqosid Extension* +
+*Hypervisor ISA* +
+*Shlcofideleg Extension* +
+*Svvptc Extension*
+
+|_1.14_ +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+_1.14_ +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0*
+
+|_Draft_ +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+_Draft_ +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified* +
+*Ratified*
+|===
+
+The following changes have been made since version 1.13 of the Machine and
+Supervisor ISAs, which, while not strictly backwards compatible, are not
+anticipated to cause software portability problems in practice:
+
+* (None yet)
+
+Additionally, the following compatible changes have been
+made to the Machine and Supervisor ISAs since version 1.13:
+
+* Defined the `mstateen0` P1P14 field.
+
+Finally, the following clarifications and document improvements have been made
+since the last document release:
+
+* (None yet)
+
 [.big]*_Preface to Version 20241017_*
 
 This document describes the RISC-V privileged architecture. This

docs/riscv-isa/src/riscv-privileged.adoc

@@ -4,8 +4,8 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Volume II - Privileged Architecture
-:revnumber: 20241017
-:revremark: This document is in Ratified state.
+:revnumber: 20241101
+//:revremark: This document is in Ratified state.
 //development: assume everything can change
 //stable: assume everything could change
 //frozen: of you implement this version you assume the risk that something might change because of the public review cycle  but we expect little to no change.
@@ -22,7 +22,7 @@ include::../docs-resources/global-config.adoc[]
 // Settings:
 :experimental:
 :reproducible:
-:imagesoutdir: images
+:imagesoutdir: {docdir}/../build/images-out
 :bibtex-file: src/resources/riscv-spec.bib
 :bibtex-order: alphabetical
 :bibtex-style: apa
@@ -100,6 +100,7 @@ include::smcntrpmf.adoc[]
 include::rnmi.adoc[]
 include::smcdeleg.adoc[]
 include::smdbltrp.adoc[]
+include::smctr.adoc[]
 include::supervisor.adoc[]
 include::sstc.adoc[]
 include::sscofpmf.adoc[]

docs/riscv-isa/src/riscv-unprivileged.adoc

@@ -4,7 +4,7 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Unprivileged Architecture
-:revnumber: 20241017
+:revnumber: 20241101
 //:revremark: Pre-release version
 :colophon:
 :preface-title: Preamble
@@ -19,7 +19,7 @@ include::../docs-resources/global-config.adoc[]
 // Settings:
 :experimental:
 :reproducible:
-:imagesoutdir: images
+:imagesoutdir: {docdir}/../build/images-out
 :bibtex-file: src/resources/riscv-spec.bib
 :bibtex-order: alphabetical
 :bibtex-style: apa

docs/riscv-isa/src/rv64.adoc

@@ -205,6 +205,10 @@ no standard HINTs will ever be defined in this subspace.
  (_rs2_=_x4_) NTL.S1 +
  (_rs2_=_x5_) NTL.ALL
 
+|SLLI |_rd_=`x0`, _rs1_=`x0`, _shamt_=31 |1|Semihosting entry marker
+
+|SRAI |_rd_=`x0`, _rs1_=`x0`, _shamt_=7 |1|Semihosting exit marker
+
 |SUB |_rd_=_x0_ |latexmath:[$2^{10}$] .16+.^| _Designated for future standard use_
 
 |AND |_rd_=_x0_ |latexmath:[$2^{10}$]
@@ -243,11 +247,11 @@ no standard HINTs will ever be defined in this subspace.
 
 |SLTIU |_rd_=_x0_ |latexmath:[$2^{17}$]
 
-|SLLI |_rd_=_x0_ |latexmath:[$2^{11}$]
+|SLLI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠31 |latexmath:[$2^{11}-1$]
 
-|SRLI |_rd_=_x0_ |latexmath:[$2^{11}$]
+|SRLI |_rd_=`x0` |latexmath:[$2^{11}$]
 
-|SRAI |_rd_=_x0_ |latexmath:[$2^{11}$]
+|SRAI |_rd_=`x0`, and either _rs1_≠``x0`` or _shamt_≠7 |latexmath:[$2^{11}-1$]
 
 |SLLIW |_rd_=_x0_ |latexmath:[$2^{10}$]
 

docs/riscv-isa/src/scalar-crypto.adoc

@@ -1,4 +1,4 @@
-[[scalar-crypto]]
+[[crypto_scalar_instructions]]
 == Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
 
 ifeval::[{RVZk} == false]