minor fixes

openhwgroup · Dec 5, 2024 · 030af2d · 030af2d
1 parent 4da0c6a
commit 030af2d
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Showing 4 changed files with 11 additions and 11 deletions.
diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc b/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc
@@ -230,7 +230,7 @@
 | PACK | pack rd, rs1, rs2 | X(rd) = X(rs2)[XLEN/2-1..0] @ X(rs1)[XLEN/2-1..0] | NONE | NONE | This instruction packs the lower halves of rs1 and rs2 into rd, with rs1 in the lower half and rs2 in the upper half. | Pack instructions 
 | PACKH | packh rd, rs1, rs2 | X(rd) = EXTZ(X(rs2)[7..0] @ X(rs1)[7..0]) | NONE | NONE | This instruction packs the least-significant bytes of rs1 and rs2 into the 16 least-significant bits of rd, zero extending the rest of rd. | Pack instructions 
 | PACKW | packw rd, rs1, rs2 | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0]) | NONE | NONE | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd. | Pack instructions 
-| ZIP | zip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
-| UNZIP | unzip rd, rs | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
+| ZIP | zip rd, rs | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];} | NONE | NONE | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions 
+| UNZIP | unzip rd, rs | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];} | NONE | NONE | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction. | Zip instructions 
 | BREV8 | brev8 rd, rs | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE | NONE | This instruction reverses the order of the bits in every byte of a register. | Bits-in-Byte-reverse
 |===
diff --git a/config/gen_from_riscv_config/cv32a65x/isa/isa.rst b/config/gen_from_riscv_config/cv32a65x/isa/isa.rst
@@ -409,9 +409,9 @@ RVZbkb Bitmanip instructions for Cryptography
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
 | PACKW     | packw rd, rs1, rs2     | X(rd) = EXTS(X(rs2)[15..0] @ X(rs1)[15..0])                                                         | NONE             | NONE               | This instruction packs the low 16 bits of rs1 and rs2 into the 32 least-significant bits of rd, sign extending the 32-bit result to the rest of rd.                                                                                                             | Pack instructions       |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| ZIP       | zip rd, rs             | foreach (i from 0 to xlen/2-1) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2];}    | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
+| ZIP       | zip rd, rs             | foreach (i from 0 to 15) { X(rd)[i << 1] = X(rs1)[i]; X(rd)[i+1 << 1] = X(rs1)[i+16];}              | NONE             | NONE               | This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction. | Zip instructions        |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
-| UNZIP     | unzip rd, rs           | foreach (i from 0 to xlen/2-1) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1];}    | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
+| UNZIP     | unzip rd, rs           | foreach (i from 0 to 15) { X(rd)[i] = X(rs1)[i << 1]; X(rd)[i+16] = X(rs1)[i+1 << 1];}              | NONE             | NONE               | This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.                                              | Zip instructions        |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
 | BREV8     | brev8 rd, rs           | foreach (i from 0 to xlen by 8) {foreach (j from 0 to 7) { X(rd)[(i<<3)+j] = X(rs)[(i<<3)+(7-j)];}} | NONE             | NONE               | This instruction reverses the order of the bits in every byte of a register.                                                                                                                                                                                    | Bits-in-Byte-reverse    |
 +-----------+------------------------+------------------------------------------+------------------+--------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
diff --git a/core/alu.sv b/core/alu.sv
@@ -278,13 +278,13 @@ module alu
     end
     // Generate zip and unzip results
     if (CVA6Cfg.IS_XLEN32) begin
-      for (n = 0; n < CVA6Cfg.XLEN / 2; n++) begin : zip_unzip_gen
+      for (n = 0; n < 16; n++) begin : zip_unzip_gen
         // Assigning lower and upper half of operand into the even and odd positions of result
         assign zip_gen[n<<1] = fu_data_i.operand_a[n];
-        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+CVA6Cfg.XLEN/2];
+        assign zip_gen[(n<<1)+1] = fu_data_i.operand_a[n+16];
         // Assigning even and odd bits of operand into lower and upper halves of result
         assign unzip_gen[n] = fu_data_i.operand_a[n<<1];
-        assign unzip_gen[n+CVA6Cfg.XLEN/2] = fu_data_i.operand_a[(n<<1)+1];
+        assign unzip_gen[n+16] = fu_data_i.operand_a[(n<<1)+1];
       end
     end
   end

diff --git a/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst b/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst
@@ -114,9 +114,9 @@ RV32 specific Instructions
 
     **Description**: This instruction places bits in the low half of the source register into the even bit positions of the destination, and bits in the high half of the source register into the odd bit positions of the destination. It is the inverse of the unzip instruction.
 
-    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+    **Pseudocode**: foreach (i from 0 to 15) {
                         X(rd)[i << 1] = X(rs1)[i]
-                        X(rd)[i+1 << 1] = X(rs1)[i+XLEN/2] 
+                        X(rd)[i+1 << 1] = X(rs1)[i+16] 
                     }
 
     **Invalid values**: NONE
@@ -129,9 +129,9 @@ RV32 specific Instructions
 
     **Description**: This instruction places the even bits of the source register into the low half of the destination, and the odd bits of the source into the high bits of the destination. It is the inverse of the zip instruction.
 
-    **Pseudocode**: foreach (i from 0 to xlen/2-1) {
+    **Pseudocode**: foreach (i from 0 to 15) {
                         X(rd)[i] = X(rs1)[i << 1]
-                        X(rd)[i+XLEN/2] = X(rs1)[i+1 << 1]
+                        X(rd)[i+16] = X(rs1)[i+1 << 1]
                     }
 
     **Invalid values**: NONE