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[RVV] CVA6 re-parametrization and MMU interface #1742

[RVV] CVA6 re-parametrization and MMU interface

[RVV] CVA6 re-parametrization and MMU interface #1742

Triggered via pull request December 4, 2024 21:46
@mp-17mp-17
opened #2652
Status Success
Total duration 59s
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verible.yml

on: pull_request_target
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1 warning
format: core/load_store_unit.sv#L214
[verible-verilog-format] reported by reviewdog 🐶 Raw Output: core/load_store_unit.sv:214:- logic [CVA6Cfg.PLEN-1:0] mmu_paddr, mmu_vaddr_plen, fetch_vaddr_plen, cva6_mmu_paddr, acc_mmu_paddr; core/load_store_unit.sv:215:- logic [ 31:0] mmu_tinst; core/load_store_unit.sv:216:- logic mmu_hs_ld_st_inst; core/load_store_unit.sv:217:- logic mmu_hlvx_inst; core/load_store_unit.sv:218:- exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; core/load_store_unit.sv:219:- logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; core/load_store_unit.sv:220:- logic [ CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; core/load_store_unit.sv:221:- core/load_store_unit.sv:222:- logic ld_valid; core/load_store_unit.sv:223:- logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; core/load_store_unit.sv:224:- logic [ CVA6Cfg.XLEN-1:0] ld_result; core/load_store_unit.sv:225:- logic st_valid; core/load_store_unit.sv:226:- logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; core/load_store_unit.sv:227:- logic [ CVA6Cfg.XLEN-1:0] st_result; core/load_store_unit.sv:228:- core/load_store_unit.sv:229:- logic [ 11:0] page_offset; core/load_store_unit.sv:230:- logic page_offset_matches; core/load_store_unit.sv:231:- core/load_store_unit.sv:232:- exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; core/load_store_unit.sv:233:- exception_t ld_ex; core/load_store_unit.sv:234:- exception_t st_ex; core/load_store_unit.sv:235:- core/load_store_unit.sv:236:- logic hs_ld_st_inst; core/load_store_unit.sv:237:- logic hlvx_inst; core/load_store_unit.sv:214:+ logic [CVA6Cfg.PLEN-1:0] core/load_store_unit.sv:215:+ mmu_paddr, mmu_vaddr_plen, fetch_vaddr_plen, cva6_mmu_paddr, acc_mmu_paddr; core/load_store_unit.sv:216:+ logic [31:0] mmu_tinst; core/load_store_unit.sv:217:+ logic mmu_hs_ld_st_inst; core/load_store_unit.sv:218:+ logic mmu_hlvx_inst; core/load_store_unit.sv:219:+ exception_t mmu_exception, cva6_mmu_exception, acc_mmu_exception; core/load_store_unit.sv:220:+ logic dtlb_hit, cva6_dtlb_hit, acc_dtlb_hit; core/load_store_unit.sv:221:+ logic [CVA6Cfg.PPNW-1:0] dtlb_ppn, cva6_dtlb_ppn, acc_dtlb_ppn; core/load_store_unit.sv:222:+ core/load_store_unit.sv:223:+ logic ld_valid; core/load_store_unit.sv:224:+ logic [CVA6Cfg.TRANS_ID_BITS-1:0] ld_trans_id; core/load_store_unit.sv:225:+ logic [ CVA6Cfg.XLEN-1:0] ld_result; core/load_store_unit.sv:226:+ logic st_valid; core/load_store_unit.sv:227:+ logic [CVA6Cfg.TRANS_ID_BITS-1:0] st_trans_id; core/load_store_unit.sv:228:+ logic [ CVA6Cfg.XLEN-1:0] st_result; core/load_store_unit.sv:229:+ core/load_store_unit.sv:230:+ logic [ 11:0] page_offset; core/load_store_unit.sv:231:+ logic page_offset_matches; core/load_store_unit.sv:232:+ core/load_store_unit.sv:233:+ exception_t misaligned_exception, cva6_misaligned_exception, acc_misaligned_exception; core/load_store_unit.sv:234:+ exception_t ld_ex; core/load_store_unit.sv:235:+ exception_t st_ex; core/load_store_unit.sv:236:+ core/load_store_unit.sv:237:+ logic hs_ld_st_inst; core/load_store_unit.sv:238:+ logic hlvx_inst;