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Pull requests: llvm/circt

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Pull requests list

Bump LLVM to aa580c2ec5eb4217c945a47a561181be7e7b1032.
#8108 opened Jan 22, 2025 by mikeurbach Loading…
[RTG][Elaboration] Support labels RTG Involving the `rtg` dialect
#8107 opened Jan 22, 2025 by maerhart Loading…
[RTG][EmitISA] Support labels RTG Involving the `rtg` dialect
#8106 opened Jan 22, 2025 by maerhart Loading…
[RTGTest] Add branch instructions RTG Involving the `rtg` dialect
#8105 opened Jan 22, 2025 by maerhart Loading…
[Pipeline] Make reset signal optional
#8104 opened Jan 22, 2025 by mortbopet Loading…
[RTG][Elaboration] Support fixed and virtual registers RTG Involving the `rtg` dialect
#8101 opened Jan 21, 2025 by maerhart Loading…
[RTG] More convenient InstructionOpInterface methods RTG Involving the `rtg` dialect
#8100 opened Jan 21, 2025 by maerhart Loading…
[FIRRTL][CAPI] add layer for firrtlTypeGetRef
#8093 opened Jan 17, 2025 by sequencer Loading…
[FIRRTL] Add circt_view intrinsic lowering to firrtl.view
#8083 opened Jan 14, 2025 by dtzSiFive • Draft
[RTG][python] fix populateDialectRTGTestSubmodule namespacing
#8078 opened Jan 13, 2025 by makslevental Loading…
3
[MemoryBanking] Bank memref::copy logically using memref::subView
#8074 opened Jan 13, 2025 by jiahanxie353 Loading…
6
[HW] Add passes to remove modules from the hierarchy and recursively expose IO of their instances
#8070 opened Jan 12, 2025 by CircuitCoder Loading…
1 task
3
[RTGTest] Add dialect materializer RTG Involving the `rtg` dialect
#8063 opened Jan 10, 2025 by maerhart Loading…
1
[RTG] Add simple linear scan register allocation pass RTG Involving the `rtg` dialect
#8058 opened Jan 9, 2025 by maerhart Loading…
4
[RTG] Add ISA assembly emission pass RTG Involving the `rtg` dialect
#8057 opened Jan 9, 2025 by maerhart Loading…
4
[RTGTest] Add a few instructions RTG Involving the `rtg` dialect
#8056 opened Jan 9, 2025 by maerhart Loading…
1
[RTGTest] Add representation for immediates RTG Involving the `rtg` dialect
#8053 opened Jan 9, 2025 by maerhart Loading…
2
[RTGTest] Improved register representation RTG Involving the `rtg` dialect
#8052 opened Jan 9, 2025 by maerhart Loading…
[HW] Enable parametric polymorphism for module parameters
#8040 opened Jan 8, 2025 by bubblepipe42 Loading…
4
[LLHD] Removing llhd-sim tests LLHD
#8036 opened Jan 7, 2025 by teqdruid Loading…
3
Convert ICE40 to BLIF
#8031 opened Jan 5, 2025 by darthscsi • Draft
[ImportVerilog] add real literal support, refine real type, and add real format support Moore
#8020 opened Dec 29, 2024 by chenbo-again • Draft
6
Add the BLIF dialect.
#8019 opened Dec 29, 2024 by darthscsi Loading…
4
Add the ICE40 dialect.
#8018 opened Dec 27, 2024 by darthscsi Loading…
11
[ImportVerilog] Support for Procedural assign statements ImportVerilog Moore
#8010 opened Dec 19, 2024 by owlxiao Loading…
3
ProTip! Updated in the last three days: updated:>2025-01-19.