HyperRAM: Add variable latency and configuration support.

[enjoy-digital]

Previous version of the core was very minimal and was not allowing enabling variable latency support or latency configuration for low HyperRAM clock frequencies.

This PR adds:

• Registers Read/Write support.
• Variable latency support to core.
• Configurable core latency.
• Software initialization to configure HyperRAM Chip and Core with variable latency and mininal latency based on SoC's sys_clk_freq.

CoreMark on Ti60 F225 with 200MHz sys_clk_freq and previous version of the core:

coremark built on Apr 10 2024 12:00:23
test 1...done
test 2...done
test 3...done
test 4...done
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 2594810342
Total time (secs): 12
Iterations/Sec   : 166
Iterations       : 2000
Compiler version : GCC10.1.0
Compiler flags   : mem:main_ram -MD -MP -O2 -march=rv32i2p0_ma -mabi=ilp32 -D__vexriscv__ -DUART_POLLING  
Memory location  : stack
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x4983
Correct operation validated. See README.md for run and reporting rules.

CoreMark on Ti60 F225 with 200MHz sys_clk_freq and current version of the core:

 coremark built on Apr 15 2024 15:54:24
test 1...done
test 2...done
test 3...done
test 4...done
2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 2697812194
Total time (secs): 13
Iterations/Sec   : 307
Iterations       : 4000
Compiler version : GCC10.1.0
Compiler flags   : mem:main_ram -MD -MP -O2 -march=rv32i2p0_ma -mabi=ilp32 -D__vexriscv__ -DUART_POLLING  
Memory location  : stack
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0x65c5
Correct operation validated. See README.md for run and reporting rules.

So 307 vs 166 Iterations/Sec so a gain of 85%.