cores/hyperbus: Fix bytes order on register writes.

enjoy-digital · Apr 12, 2024 · b192103 · b192103
1 parent fb519ac
commit b192103
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Showing 2 changed files with 7 additions and 4 deletions.
diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py
@@ -44,6 +44,9 @@ def __init__(self, pads, latency=6, sys_clk_freq=None, with_csr=True):
         self.reg_write_data = Signal(16)
         self.reg_read_data  = Signal(16)
 
+        if with_csr:
+            self.add_csr()
+
         self.reg_debug = CSRStatus(32)
 
         # # #
@@ -211,7 +214,7 @@ def __init__(self, pads, latency=6, sys_clk_freq=None, with_csr=True):
             # Wait for 6*2 cycles...
             If(cycles == (6*2 - 1),
                 If(reg_write_req,
-                    NextValue(sr, Cat(Signal(40), self.reg_write_data[:8])),
+                    NextValue(sr, Cat(Signal(40), self.reg_write_data[8:])),
                     NextState("REG-WRITE-0")
                 ).Else(
                     NextState("WAIT-LATENCY")
@@ -226,7 +229,7 @@ def __init__(self, pads, latency=6, sys_clk_freq=None, with_csr=True):
             dq.oe.eq(1),
             # Wait for 2 cycles...
             If(cycles == (2 - 1),
-                NextValue(sr, Cat(Signal(40), self.reg_write_data[8:])),
+                NextValue(sr, Cat(Signal(40), self.reg_write_data[:8])),
                 NextState("REG-WRITE-1")
             )
         )
@@ -315,7 +318,7 @@ def add_csr(self):
         self.reg_control = CSRStorage(fields=[
             CSRField("write", offset=0, size=1, pulse=True, description="Issue Register Write."),
             CSRField("read",  offset=1, size=1, pulse=True, description="Issue Register Read."),
-            CSRField("reg",   offset=8, size=4, values=[
+            CSRField("addr",  offset=8, size=4, values=[
                 ("``0``", "Identification Register 0 (Read Only)."),
                 ("``1``", "Identification Register 1 (Read Only)."),
                 ("``2``", "Configuration Register 0."),

diff --git a/test/test_hyperbus.py b/test/test_hyperbus.py
@@ -103,7 +103,7 @@ def hyperram_gen(dut):
             clk     = "___--__--__--__--___________"
             cs_n    = "--________________----------"
             dq_oe   = "__----------------__________"
-            dq_o    = "0060000100000034120000000000"
+            dq_o    = "0060000100000012340000000000"
             rwds_oe = "____________________________"
             rwds_o  = "____________________________"
             for i in range(3):