litex: gen: fhdl: verilog.py: bring back lower_complex_slices()

bring back lower_complex_slices() as it is sometimes needed.
for example, when a Slice of a Cat() is done.

Signed-off-by: Fin Maaß <[email protected]>

litex/gen/fhdl/verilog.py

@@ -23,6 +23,7 @@
 from migen.fhdl.structure   import *
 from migen.fhdl.structure   import _Operator, _Slice, _Assign, _Fragment
 from migen.fhdl.tools       import *
+from migen.fhdl.tools       import _apply_lowerer, _Lowerer
 from migen.fhdl.conv_output import ConvOutput
 from migen.fhdl.specials    import Instance, Memory
 
@@ -415,6 +416,25 @@ def _generate_specials(name, overrides, specials, namespace, add_data_file, attr
         r += pr
     return r
 
+# ------------------------------------------------------------------------------------------------ #
+#                                       LOWERER                                                    #
+# ------------------------------------------------------------------------------------------------ #
+
+class _ComplexSliceLowerer(_Lowerer):
+    def visit_Slice(self, node):
+        if not (isinstance(node.value, Signal) or isinstance(node.value, _Slice)):
+            slice_proxy = Signal(value_bits_sign(node.value))
+            if self.target_context:
+                a = _Assign(node.value, slice_proxy)
+            else:
+                a = _Assign(slice_proxy, node.value)
+            self.comb.append(self.visit_Assign(a))
+            node = _Slice(slice_proxy, node.start, node.stop)
+        return NodeTransformer.visit_Slice(self, node)
+
+def lower_complex_slices(f):
+    return _apply_lowerer(_ComplexSliceLowerer(), f)
+
 # ------------------------------------------------------------------------------------------------ #
 #                                    FHDL --> VERILOG                                              #
 # ------------------------------------------------------------------------------------------------ #