core/hyperbus: Start testing Register writes.

enjoy-digital · Apr 11, 2024 · 441d05e · 441d05e
1 parent 59756b4
commit 441d05e
Showing 1 changed file with 29 additions and 0 deletions.
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
@@ -175,6 +175,8 @@ __attribute__((__used__)) int main(int i, char **c)
 
         sdr_ok = 1;
 
+    uint16_t config_reg_0;
+
 	/* HyperRAM Register access test */
 	hyperram_reg_control_write(
 		0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
@@ -199,6 +201,7 @@ __attribute__((__used__)) int main(int i, char **c)
 	);
 	while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
 	printf("Configuration Register 0  : %08lx\n", hyperram_reg_rdata_read());
+	config_reg_0 = hyperram_reg_rdata_read();
 
 	hyperram_reg_control_write(
 		0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
@@ -208,10 +211,36 @@ __attribute__((__used__)) int main(int i, char **c)
 	while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
 	printf("Configuration Register 1  : %08lx\n", hyperram_reg_rdata_read());
 
+	config_reg_0 &= ~(1 << 3); /* Enable Variable Latency */
+	printf("New config_reg_0: %08lx\n", config_reg_0);
+	hyperram_reg_wdata_write(config_reg_0);
+	hyperram_reg_control_write(
+		1 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
+		0 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET  |
+		2 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
+	);
+	while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_WRITE_DONE_OFFSET)) == 0);
+
 	printf("reg_control: %x\n", hyperram_reg_control_read());
 	printf("reg_status:  %x\n", hyperram_reg_status_read());
 	printf("reg_debug:   %x\n", hyperram_reg_debug_read());
 
+	hyperram_reg_control_write(
+		0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
+		1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET  |
+		2 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
+	);
+	while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
+	printf("Configuration Register 0 after update : %08lx\n", hyperram_reg_rdata_read());
+
+	hyperram_reg_control_write(
+		0 << CSR_HYPERRAM_REG_CONTROL_WRITE_OFFSET |
+		1 << CSR_HYPERRAM_REG_CONTROL_READ_OFFSET  |
+		3 << CSR_HYPERRAM_REG_CONTROL_REG_OFFSET
+	);
+	while ((hyperram_reg_status_read() & (1 << CSR_HYPERRAM_REG_STATUS_READ_DONE_OFFSET)) == 0);
+	printf("Configuration Register 1  : %08lx\n", hyperram_reg_rdata_read());
+
 
 #if defined(CSR_ETHMAC_BASE) || defined(MAIN_RAM_BASE) || defined(CSR_SPIFLASH_CORE_BASE)
     printf("--========== \e[1mInitialization\e[0m ============--\n");