soc/add_etherbone: Revert sys_clk domain renaming when ethmac is disa…

…bled.
enjoy-digital · Feb 9, 2024 · 1b32d8a · 1b32d8a
1 parent afcf78f
commit 1b32d8a
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1844,7 +1844,9 @@ def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", data_width=8,
             # Use PHY's eth_tx/eth_rx clock domains.
             ethcore = ClockDomainsRenamer({
                 "eth_tx": phy_cd + "_tx",
-                "eth_rx": phy_cd + "_rx"})(ethcore)
+                "eth_rx": phy_cd + "_rx",
+                "sys"   : {True: "sys", False: phy_cd + "_rx"}[with_ethmac],
+            })(ethcore)
         self.add_module(name=f"ethcore_{name}", module=ethcore)
 
         etherbone_cd = "sys"