Merge branch 'master' into jtag

# Conflicts:
#	litex/soc/cores/cpu/vexriscv_smp/core.py

CHANGES.md

@@ -1,5 +1,33 @@
-[> Changes since 2023.08
+[> Changes since 2023.12
 ------------------------
+	[> Fixed
+	--------
+	- integration/soc               : Fixed typo in cpu mem_bus axi-via-wb downconvert
+	- interconnect/ahb/AHB2Wishbone : Fixed size check that was too restrictive.
+	- liteeth/phy/gw5rgmii          : Fixed Clk assignments.
+	- build/efinix/programmer       : Updated for compatibility with latest Efinity versions.
+	- litespi/software:             : Fixed SPI Flash Clk Divider computation when with L2 Cache.
+	- litepcie/us(p)pciephy         : Fixed x8 / 256-bit wide case.
+
+	[> Added
+	--------
+	- build/openfpgaloader          : Added kwargs support to flash for specific/less common cases.
+	- cpu/gowin_emcu                : Improved/Cleaned-up.
+	- interconnect/ahb              : Added data_width/address_width parameters.
+	- interconnect/ahb              : Added proper byte/sel support to AHB2Wishbone.
+	- cpu/gowin_ae350               : Added initial support.
+	- cpu/naxriscv                  : Updated arch definition and added rvc configuration parameters.
+	- cpu/vexriscv_smp              : Added csr/clint/plic base address configuration parameters.
+	- liteeth/phy                   : Added 7-Series/Ultrascale(+) 2500BaseX PHYs.
+	- litespi/sdrphy:               : Allowed flash parameter to be None.
+	- litespi/integration           : Improved integration and simplifications.
+	- export/builder                : Add import/merge of Sub-SoCs .json files.
+
+	[> Changed
+	----------
+
+[> 2023.12, released on December 25th 2023
+------------------------------------------
 	[> Fixed
 	--------
 	- liteeth/arp           : Fixed response on table update.
@@ -30,16 +58,20 @@
 	- litepcie              : Simplify/Cleanup Ultrascale(+) integration and allow .xci generation from .tcl.
 	- litepcie              : Initial 64-bit DMA suppport.
 	- bios                  : Added bios_format / --bios-format to allow enabling float/double printf.
-	- soc/cores/clock       : Added proper clock feedback support on Efinix TRIONPLL.
+	- soc/cores/clock       : Added proper clock feedback support on Efinix TRIONPLL/TITANIUMPLL.
 	- liteiclink/phy        : Added Efinix support/examples on Trion/Titanium.
 	- liteiclink/serwb      : Reused Etherbone from LiteEth to avoid code duplication.
 	- interconnect          : Added 64-bit support to Wishbone/AXI-Lite/AXI.
 	- jtag                  : Fixed firmware upload over JTAG-UART.
 	- jtag                  : Improved speed (~X16) on JTABone/JTAGUART on all supported devices (Xilinx, Altera, Efinix, etc...)
+	- litesata/phy          : Added GTHE4 support on Ultrascale+.
+	- litex_boards          : Added Machdyne's Mozart with the Sechzig ML1 module support.
+	- liteiclink            : Added clk_ratio of 1:2, 1:4 on Efinix/SerWB to make clocking more flexible.
 
 	[> Changed
 	----------
-	- build/osfpga: Removed initial support (would need feedbacks/updates).
+	- build/osfpga          : Removed initial support (would need feedbacks/updates).
+	- python3               : Updated minimum python3 version to 3.7 (To allow more than 255 arguments in functions).
 
 [> 2023.08, released on September 14th 2023
 -------------------------------------------

README.md

@@ -1,7 +1,7 @@
 <p align="center"><img src="https://raw.githubusercontent.com/enjoy-digital/litex/master/doc/litex.png"></p>
 
 ```
-             Copyright 2012-2023 / Enjoy-Digital & LiteX developers
+             Copyright 2012-2024 / Enjoy-Digital & LiteX developers
 ```
 [![](https://github.com/enjoy-digital/litex/workflows/ci/badge.svg)](https://github.com/enjoy-digital/litex/actions)
 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)

litex/build/efinix/efinity.py

@@ -361,8 +361,19 @@ def run_script(self, script):
             "--io_weak_pullup",           "on",
             "--enable_roms",              "on",
             "--mode",                     self.platform.spi_mode,
-            "--width",                    "1",
+            "--width",                    self.platform.spi_width,
             "--enable_crc_check",         "on"
         ], common.colors)
         if r != 0:
             raise OSError("Error occurred during efx_pgm execution.")
+
+        # BINARY
+        os.environ['EFXPGM_HOME'] = self.efinity_path + "/pgm"
+        r = tools.subprocess_call_filtered([self.efinity_path + "/bin/python3",
+            self.efinity_path + "/pgm/bin/efx_pgm/export_bitstream.py",
+            "hex_to_bin",
+            f"{self._build_name}.hex",
+            f"{self._build_name}.bin"
+        ], common.colors)
+        if r != 0:
+           raise OSError("Error occurred during export_bitstream execution.")

litex/build/efinix/ifacewriter.py

@@ -281,15 +281,9 @@ def generate_pll(self, block, partnumber, verbose=True):
             if block["version"] == "V3":
                 cmd += 'design.gen_pll_ref_clock("{}", pll_res="{}", refclk_src="EXTERNAL", refclk_name="{}", ext_refclk_no="{}", ext_refclk_type="LVDS_RX")\n\n' \
                         .format(name, block["resource"], block["input_clock_pad"], block["clock_no"])
-                cmd += 'design.set_property("{}","FEEDBACK_MODE","CORE","PLL")\n\n'.format(name)
 
             else:
                 cmd += 'design.set_property("{}","EXT_CLK","EXT_CLK{}","PLL")\n'.format(name, block["clock_no"])
-                if block["feedback"] != -1:
-                    cmd += 'design.set_property("{}","FEEDBACK_MODE","{}","PLL")\n'.format(name, "CORE" if block["feedback"] == 0 else "LOCAL")
-                    cmd += 'design.set_property("{}","FEEDBACK_CLK","CLK{}","PLL")\n'.format(name, block["feedback"])
-                else:
-                    cmd += 'design.set_property("{}","FEEDBACK_MODE","INTERNAL","PLL")\n'.format(name)
                 cmd += 'design.assign_resource("{}","{}","PLL")\n'.format(name, block["resource"])
 
 
@@ -329,7 +323,14 @@ def generate_pll(self, block, partnumber, verbose=True):
             else:
                 cmd += 'design.set_property("{}","CLKOUT{}_PHASE_SETTING","{}","PLL")\n'.format(name, i, clock[2] // 45)
 
-        if block["feedback"] == -1:
+        # Titanium has always a feedback (local: CLK0, CORE: any output)
+        if block["version"] == "V3":
+            feedback_clk = block["feedback"]
+            cmd += 'design.set_property("{}", "FEEDBACK_MODE", "{}", "PLL")\n'.format(name, "LOCAL" if feedback_clk < 1 else "CORE")
+            cmd += 'design.set_property("{}", "FEEDBACK_CLK", "CLK{}", "PLL")\n'.format(name, 0 if feedback_clk < 1 else feedback_clk)
+
+        # auto_calc_pll_clock is always working with Titanium and only working when feedback is unused for Trion
+        if block["feedback"] == -1 or block["version"] == "V3":
             cmd += "target_freq = {\n"
             for i, clock in enumerate(block["clk_out"]):
                 cmd += '    "CLKOUT{}_FREQ": "{}",\n'.format(i, clock[1] / 1e6)
@@ -338,6 +339,9 @@ def generate_pll(self, block, partnumber, verbose=True):
                     cmd += '    "CLKOUT{}_DYNPHASE_EN": "1",\n'.format(i)
             cmd += "}\n"
 
+            if block["version"] == "V1_V2":
+                cmd += 'design.set_property("{}","FEEDBACK_MODE","INTERNAL","PLL")\n'.format(name)
+
             cmd += 'calc_result = design.auto_calc_pll_clock("{}", target_freq)\n'.format(name)
             cmd += 'for c in calc_result:\n'
             cmd += '    print(c)\n'
@@ -349,6 +353,8 @@ def generate_pll(self, block, partnumber, verbose=True):
                 cmd += 'design.set_property("{}","CLKOUT{}_PHASE","{}","PLL")\n'.format(name, i, clock[2])
                 #cmd += 'design.set_property("{}","CLKOUT{}_FREQ","{}","PLL")\n'.format(name, i, clock[2])
                 cmd += 'design.set_property("{}","CLKOUT{}_DIV","{}","PLL")\n'.format(name, i, block[f"CLKOUT{i}_DIV"])
+            cmd += 'design.set_property("{}","FEEDBACK_MODE","{}","PLL")\n'.format(name, "LOCAL" if block["feedback"] == 0 else "CORE")
+            cmd += 'design.set_property("{}","FEEDBACK_CLK","CLK{}","PLL")\n'.format(name, block["feedback"])
 
         if "extra" in block:
             cmd += block["extra"]
@@ -358,17 +364,19 @@ def generate_pll(self, block, partnumber, verbose=True):
             cmd += 'print("#### {} ####")\n'.format(name)
             cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name)
             cmd += 'pprint.pprint(clksrc_info)\n'
-            cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE"]\n'
+            cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE", "FEEDBACK_MODE", "FEEDBACK_CLK"]\n'
             for i, clock in enumerate(block["clk_out"]):
                 cmd += 'clock_source_prop += ["CLKOUT{}_FREQ", "CLKOUT{}_PHASE", "CLKOUT{}_EN"]\n'.format(i, i, i)
             cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name)
             cmd += 'pprint.pprint(prop_map)\n'
 
-            for i, clock in enumerate(block["clk_out"]):
-                cmd += '\nfreq = float(prop_map["CLKOUT{}_FREQ"])\n'.format(i)
-                cmd += 'if freq != {}:\n'.format(clock[1]/1e6)
-                cmd += '    print("ERROR: CLKOUT{} configured for {}MHz is {{}}MHz".format(freq))\n'.format(i, clock[1]/1e6)
-                cmd += '    exit("PLL ERROR")\n'
+            # Efinix python API is buggy for Trion devices when a feedback is defined...
+            if block["version"] == "V3" or (block["version"] == "V1_V2" and block["feedback"] == -1):
+                for i, clock in enumerate(block["clk_out"]):
+                    cmd += '\nfreq = float(prop_map["CLKOUT{}_FREQ"])\n'.format(i)
+                    cmd += 'if freq != {}:\n'.format(clock[1]/1e6)
+                    cmd += '    print("ERROR: CLKOUT{} configured for {}MHz is {{}}MHz".format(freq))\n'.format(i, clock[1]/1e6)
+                    cmd += '    exit("PLL ERROR")\n'
 
         cmd += "\n#---------- END PLL {} ---------\n\n".format(name)
         return cmd

litex/build/efinix/platform.py

@@ -23,13 +23,14 @@ class EfinixPlatform(GenericPlatform):
 
     _supported_toolchains = ["efinity"]
 
-    def __init__(self, *args, iobank_info=None, toolchain="efinity", spi_mode="active", **kwargs):
+    def __init__(self, *args, iobank_info=None, toolchain="efinity", spi_mode="active", spi_width="1", **kwargs):
         GenericPlatform.__init__(self, *args, **kwargs)
 
         self.timing_model = self.device[-2:]
         self.device       = self.device[:-2]
         self.iobank_info  = iobank_info
         self.spi_mode     = spi_mode
+        self.spi_width    = spi_width
         if self.device[:2] == "Ti":
             self.family = "Titanium"
         else:

litex/build/efinix/programmer.py

@@ -28,7 +28,8 @@ def __init__(self, cable_name=""):
         os.environ["EFINITY_HOME"] = self.efinity_path
 
     def load_bitstream(self, bitstream_file, cable_suffix=""):
-        os.environ['EFXPGM_HOME'] = self.efinity_path + '/pgm'
+        os.environ['EFXPGM_HOME'] = self.efinity_path + "/pgm"
+        os.environ["EFXDBG_HOME"] = self.efinity_path + "/debugger"
         if (subprocess.call([self.efinity_path + '/bin/python3', self.efinity_path +
                    '/pgm/bin/efx_pgm/ftdi_program.py', bitstream_file,
                    "-m", "jtag"], env=os.environ.copy()) != 0):

litex/build/gowin/common.py

@@ -7,6 +7,8 @@
 from migen.fhdl.module import Module
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.gen import *
+
 from litex.build.io import *
 
 # Gowin AsyncResetSynchronizer ---------------------------------------------------------------------
@@ -58,7 +60,9 @@ def __init__(self, i1, i2, o, clk):
             i_CLK = clk,
             i_D0  = i1,
             i_D1  = i2,
+            i_TX  = 0,
             o_Q0  = o,
+            o_Q1  = Open(),
         )
 
 class GowinDDROutput:

litex/build/gowin/gowin.py

@@ -26,6 +26,7 @@ class GowinToolchain(GenericToolchain):
     def __init__(self):
         super().__init__()
         self.options = {}
+        self.additional_cst_commands = []
 
     def finalize(self):
         if self.platform.verilog_include_paths:
@@ -108,6 +109,8 @@ def _search_pin_entry(pin_lst, pin_name):
         if self.named_pc:
             cst.extend(self.named_pc)
 
+        cst.extend(self.additional_cst_commands)
+
         tools.write_to_file(f"{self._build_name}.cst", "\n".join(cst))
         return (f"{self._build_name}.cst", "CST")
 

litex/build/gowin/platform.py

@@ -43,3 +43,6 @@ def get_verilog(self, *args, special_overrides=dict(), **kwargs):
 
     def build(self, *args, **kwargs):
         return self.toolchain.build(self, *args, **kwargs)
+
+    def add_false_path_constraint(self, from_, to):
+        pass

litex/build/openfpgaloader.py

@@ -13,31 +13,66 @@ class OpenFPGALoader(GenericProgrammer):
     needs_bitreverse = False
 
     def __init__(self, board="", cable="", freq=0, fpga_part="", index_chain=None):
+        # openFPGALoader base command.
         self.cmd = ["openFPGALoader"]
+
+        # Specify FPGA board.
         if board:
             self.cmd += ["--board", board]
+
+        # Specify FPGA part/device.
         if fpga_part:
             self.cmd += ["--fpga-part", fpga_part]
+
+        # Specify programmation cable.
         if cable:
             self.cmd += ["--cable", cable]
+
+        # Specify programmation frequency.
         if freq:
             self.cmd += ["--freq", str(int(float(freq)))]
+
+        # Specify index in the JTAG chain.
         if index_chain is not None:
             self.cmd += ["--index-chain", str(int(index_chain))]
 
     def load_bitstream(self, bitstream_file):
+        # Load base command.
         cmd = self.cmd + ["--bitstream", bitstream_file]
+
+        # Execute command.
         self.call(cmd)
 
-    def flash(self, address, data_file, external=False, unprotect_flash=False, verify=False):
+    def flash(self, address, data_file, external=False, unprotect_flash=False, verify=False, **kwargs):
+        # Flash base command.
         cmd = self.cmd + ["--write-flash", "--bitstream", data_file]
+
+        # Flash Internal/External selection.
         if external:
             cmd += ["--external-flash"]
+
+        # Flash Offset.
         if address:
             cmd += ["--offset"]
             cmd += [str(address)]
+
+        # Flash Unprotect.
         if unprotect_flash:
             cmd += ["--unprotect-flash"]
+
+        # Flash Verify.
         if verify:
             cmd += ["--verify"]
-        self.call(cmd)
+
+        # Handle kwargs for specific, less common cases.
+        for key, value in kwargs.items():
+            cmd.append(f"--{key.replace('_', '-')}")
+            if value is not None:
+                cmd.append(str(value))
+
+        # Execute Command.
+        try:
+            self.call(cmd)
+        except OSError as e:
+            print(' '.join(cmd))
+            raise

litex/soc/cores/clock/efinix.py

@@ -88,7 +88,7 @@ def register_clkin(self, clkin, freq, name="", refclk_name="", lvds_input=False)
             self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))
             self.platform.get_pll_resource(pll_res)
         else:
-            block["input_clock"]  = "INTERNAL"
+            block["input_clock"]  = "INTERNAL" if self.type == "TITANIUMPLL" else "CORE"
             block["resource"]     = self.platform.get_free_pll_resource()
             block["input_signal"] = name
             self.logger.info("Clock source: {}".format(block["input_clock"]))
@@ -240,23 +240,24 @@ def compute_config(self):
                             # no solution found for this clk: params are uncompatibles
                             if found == False:
                                 break
-                        if len(cx_list) == 2:
-                            params_list.append([n, m, o, c, cx_list[0], cx_list[1]])
+                        if len(cx_list) == n_out:
+                            params_list.append([n, m, o, c, cx_list])
         vco_max_freq = 0
         o_div_max    = 0
         params_list2 = []
         for p in params_list:
-            (n, m, o, c, c0, c1) = p
+            (n, m, o, c, cx_list) = p
             fpfd_tmp             = clk_in_freq / n
             fvco_tmp             = fpfd_tmp * m * o * c
-            if o > o_div_max:
-                o_div_max = o
             # Interface designer always select high VCO freq
             if fvco_tmp > vco_max_freq:
                 vco_max_freq = fvco_tmp
                 params_list2.clear()
+                o_div_max = 0
             fpll_tmp = fvco_tmp / o
             if fvco_tmp == vco_max_freq:
+                if o > o_div_max:
+                    o_div_max = o
                 params_list2.append({
                     "fvco" : fvco_tmp,
                     "fpll" : fpll_tmp,
@@ -265,8 +266,7 @@ def compute_config(self):
                     "N"    : n,
                     "O"    : o,
                     "Cfbk" : c,
-                    "c0"   : c0,
-                    "c1"   : c1,
+                     **{f"c{n}" : cx_list[n] for n in range(n_out)},
                 })
 
         # Again: Interface Designer prefers high O divider.

litex/soc/cores/cpu/cortex_m3/core.py

@@ -5,8 +5,6 @@
 # Copyright (c) 2022 Florent Kermarrec <[email protected]>
 # SPDX-License-Identifier: BSD-2-Clause
 
-import os
-
 from migen import *
 
 from litex.gen import *

litex/soc/cores/cpu/gowin_ae350/__init__.py

@@ -0,0 +1 @@
+from litex.soc.cores.cpu.gowin_ae350.core import GowinAE350

litex/soc/cores/cpu/gowin_ae350/boot-helper.S

@@ -0,0 +1,4 @@
+	.section .text, "ax", @progbits
+	.global boot_helper
+boot_helper:
+	jr x13