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reapply 'C++20 support'
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Signed-off-by: Thomas Frank <[email protected]>
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@ThoFrank
ThoFrank committed Nov 25, 2024
1 parent bef4728 commit 6f1c324
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Showing 14 changed files with 121 additions and 121 deletions.
4 changes: 2 additions & 2 deletions ...es/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/SystemTimer/SystemTimer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -52,9 +52,9 @@ void initSystemTimer()
LPIT0->TMR[0].TVAL = 0xFFFFFFFFU;
LPIT0->SETTEN = 0x1U;

DEMCR |= 0x01000000U;
DEMCR = DEMCR | 0x01000000U;
DWT_CYCCNT = 0;
DWT_CTRL |= 0x00000001U;
DWT_CTRL = DWT_CTRL | 0x00000001U;

state.ticks = 0; // General ticks counter, never overflows
state.lastDwt = 0;
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2 changes: 1 addition & 1 deletion executables/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/adc/AnalogInput.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ void AnalogInput::init()
&analogInputScaleConfiguration[0]);

SIM->ADCOPT = 0U;
SIM->CHIPCTL &= ~SIM_CHIPCTL_PDB_BB_SEL_MASK;
SIM->CHIPCTL = SIM->CHIPCTL & ~SIM_CHIPCTL_PDB_BB_SEL_MASK;

(void)fAdc0.init();

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12 changes: 6 additions & 6 deletions platforms/s32k1xx/bsp/bspAdc/include/adc/Adc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ void Adc<AdcResolution, AdcConfiguration, maxChannels>::enableChannel(
fAdc.SC1[channel] = extInput + isrMask;
if (0U == channel)
{
uint32_t volatile timeout = 0;
uint32_t timeout = 0;
do
{
timeout++;
Expand All @@ -79,7 +79,7 @@ void Adc<AdcResolution, AdcConfiguration, maxChannels>::enableChannel(
break;
}
} while ((fAdc.SC1[0] & (COCO)) == 0);
ESR_UNUSED volatile uint32_t a = fAdcInResolution(fAdc.R[0]);
ESR_UNUSED uint32_t a = fAdcInResolution(fAdc.R[0]);
}
}
}
Expand Down Expand Up @@ -116,7 +116,7 @@ bsp::BspReturnCode Adc<AdcResolution, AdcConfiguration, maxChannels>::init()
fAdc.SC2 = 0;
fAdc.SC3 = 0x87UL;

uint32_t volatile timeout = 0;
uint32_t timeout = 0;
do
{
timeout++;
Expand Down Expand Up @@ -248,7 +248,7 @@ bsp::BspReturnCode Adc<AdcResolution, AdcConfiguration, maxChannels>::getValueSy
ESR_UNUSED volatile uint32_t a = fAdc.R[0];
fAdc.SC1[0] = phChannel;

uint32_t volatile timeout = 0;
uint32_t timeout = 0;
do
{
timeout++;
Expand Down Expand Up @@ -277,11 +277,11 @@ bsp::BspReturnCode Adc<AdcResolution, AdcConfiguration, maxChannels>::dma(bool a
ESR_UNUSED volatile uint32_t a = fAdc.R[0];
if (true == active)
{
fAdc.SC2 |= (1 << 3);
fAdc.SC2 = fAdc.SC2 | (1 << 3);
}
else
{
fAdc.SC2 &= ~(1 << 3);
fAdc.SC2 = fAdc.SC2 & ~(1 << 3);
}
return bsp::BSP_OK;
}
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54 changes: 27 additions & 27 deletions platforms/s32k1xx/bsp/bspClock/src/clockConfig.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -97,72 +97,72 @@ void enablePeripheralClocks(void)
#endif
#ifdef PCC_FTM3_INDEX
PCC->PCCn[PCC_FTM3_INDEX] = CLOCK_SOURCE_FTM3;
PCC->PCCn[PCC_FTM3_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM3_INDEX] = PCC->PCCn[PCC_FTM3_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_ADC1_INDEX
PCC->PCCn[PCC_ADC1_INDEX] = CLOCK_SOURCE_ADC1;
PCC->PCCn[PCC_ADC1_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_ADC1_INDEX] = PCC->PCCn[PCC_ADC1_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_FlexCAN2_INDEX
PCC->PCCn[PCC_FlexCAN2_INDEX] = 0xC0000000U;
#endif
PCC->PCCn[PCC_LPSPI0_INDEX] = CLOCK_SOURCE_LPSPI0;
PCC->PCCn[PCC_LPSPI0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPSPI0_INDEX] = PCC->PCCn[PCC_LPSPI0_INDEX] | 0xC0000000U;
#ifdef PCC_LPSPI1_INDEX
PCC->PCCn[PCC_LPSPI1_INDEX] = CLOCK_SOURCE_LPSPI1;
PCC->PCCn[PCC_LPSPI1_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPSPI1_INDEX] = PCC->PCCn[PCC_LPSPI1_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_LPSPI2_INDEX
PCC->PCCn[PCC_LPSPI2_INDEX] = CLOCK_SOURCE_LPSPI2;
PCC->PCCn[PCC_LPSPI2_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPSPI2_INDEX] = PCC->PCCn[PCC_LPSPI2_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_PDB1_INDEX
PCC->PCCn[PCC_PDB1_INDEX] = 0xC0000000U;
#endif
PCC->PCCn[PCC_CRC_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_PDB0_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_LPIT_INDEX] = CLOCK_SOURCE_LPIT;
PCC->PCCn[PCC_LPIT_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPIT_INDEX] = PCC->PCCn[PCC_LPIT_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_FTM0_INDEX] = CLOCK_SOURCE_FTM0;
PCC->PCCn[PCC_FTM0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM0_INDEX] = PCC->PCCn[PCC_FTM0_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_FTM1_INDEX] = CLOCK_SOURCE_FTM1;
PCC->PCCn[PCC_FTM1_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM1_INDEX] = PCC->PCCn[PCC_FTM1_INDEX] | 0xC0000000U;
#ifdef PCC_FTM2_INDEX
PCC->PCCn[PCC_FTM2_INDEX] = CLOCK_SOURCE_FTM2;
PCC->PCCn[PCC_FTM2_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM2_INDEX] = PCC->PCCn[PCC_FTM2_INDEX] | 0xC0000000U;
#endif
PCC->PCCn[PCC_ADC0_INDEX] = CLOCK_SOURCE_ADC0;
PCC->PCCn[PCC_ADC0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_ADC0_INDEX] = PCC->PCCn[PCC_ADC0_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_RTC_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_LPTMR0_INDEX] = CLOCK_SOURCE_LPTMR0;
PCC->PCCn[PCC_LPTMR0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPTMR0_INDEX] = PCC->PCCn[PCC_LPTMR0_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_PORTA_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_PORTB_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_PORTC_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_PORTD_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_PORTE_INDEX] = 0xC0000000U;
PCC->PCCn[PCC_FlexIO_INDEX] = CLOCK_SOURCE_FLEXIO;
PCC->PCCn[PCC_FlexIO_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FlexIO_INDEX] = PCC->PCCn[PCC_FlexIO_INDEX] | 0xC0000000U;
#ifdef PCC_EWM_INDEX
PCC->PCCn[PCC_EWM_INDEX] = 0xC0000000U;
#endif
PCC->PCCn[PCC_LPI2C0_INDEX] = CLOCK_SOURCE_LPI2C0;
PCC->PCCn[PCC_LPI2C0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPI2C0_INDEX] = PCC->PCCn[PCC_LPI2C0_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_LPUART0_INDEX] = CLOCK_SOURCE_LPUART0;
PCC->PCCn[PCC_LPUART0_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPUART0_INDEX] = PCC->PCCn[PCC_LPUART0_INDEX] | 0xC0000000U;
PCC->PCCn[PCC_LPUART1_INDEX] = CLOCK_SOURCE_LPUART1;
PCC->PCCn[PCC_LPUART1_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPUART1_INDEX] = PCC->PCCn[PCC_LPUART1_INDEX] | 0xC0000000U;
#ifdef PCC_LPUART2_INDEX
PCC->PCCn[PCC_LPUART2_INDEX] = CLOCK_SOURCE_LPUART2;
PCC->PCCn[PCC_LPUART2_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_LPUART2_INDEX] = PCC->PCCn[PCC_LPUART2_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_FTM4_INDEX
PCC->PCCn[PCC_FTM4_INDEX] = CLOCK_SOURCE_FTM4;
PCC->PCCn[PCC_FTM4_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM4_INDEX] = PCC->PCCn[PCC_FTM4_INDEX] | 0xC0000000U;
#endif
#ifdef PCC_FTM5_INDEX
PCC->PCCn[PCC_FTM5_INDEX] = CLOCK_SOURCE_FTM5;
PCC->PCCn[PCC_FTM5_INDEX] |= 0xC0000000U;
PCC->PCCn[PCC_FTM5_INDEX] = PCC->PCCn[PCC_FTM5_INDEX] | 0xC0000000U;
#endif
PCC->PCCn[PCC_CMP0_INDEX] = 0xC0000000U;
#ifdef PCC_CMU0_INDEX
Expand All @@ -177,7 +177,7 @@ void sircStart()
{
do
{
SCG->SIRCCSR |= SCG_SIRCCSR_SIRCEN_MASK;
SCG->SIRCCSR = SCG->SIRCCSR | SCG_SIRCCSR_SIRCEN_MASK;
} while (0 == (SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK));
}

Expand Down Expand Up @@ -213,7 +213,7 @@ void fircStart()
{
do
{
SCG->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCERR_MASK;
SCG->FIRCCSR = SCG->FIRCCSR | (SCG_FIRCCSR_FIRCEN_MASK | SCG_FIRCCSR_FIRCERR_MASK);
} while (0 == (SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK));
}

Expand Down Expand Up @@ -250,13 +250,13 @@ void spllStart()
{
do
{
SCG->SPLLCSR |= SCG_SPLLCSR_SPLLEN_MASK | SCG_SPLLCSR_SPLLERR_MASK;
SCG->SPLLCSR = SCG->SPLLCSR | (SCG_SPLLCSR_SPLLEN_MASK | SCG_SPLLCSR_SPLLERR_MASK);
} while (0 == (SCG->SPLLCSR & SCG_SPLLCSR_SPLLVLD_MASK));
}

void spllStop()
{
SCG->SPLLCSR &= ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);
SCG->SPLLCSR = SCG->SPLLCSR & ~(SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);
do
{
SCG->SPLLCSR = SCG_SPLLCSR_SPLLERR_MASK;
Expand All @@ -279,7 +279,7 @@ void spllSysClk()
SysTick->LOAD = 80000 - 1;
}

void spllMon() { SCG->SPLLCSR |= SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK; }
void spllMon() { SCG->SPLLCSR = SCG->SPLLCSR | (SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); }

bool isSpllSysClk() { return (SCG->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0; }

Expand All @@ -290,13 +290,13 @@ void soscStart()
{
do
{
SCG->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK | SCG_SOSCCSR_SOSCERR_MASK;
SCG->SOSCCSR = SCG->SOSCCSR | (SCG_SOSCCSR_SOSCEN_MASK | SCG_SOSCCSR_SOSCERR_MASK);
} while (0 == (SCG->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK));
}

void soscStop()
{
SCG->SOSCCSR &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
SCG->SOSCCSR = SCG->SOSCCSR & ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
do
{
SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
Expand All @@ -309,7 +309,7 @@ void soscConfig()
SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(_SOSCDIV2) | SCG_SOSCDIV_SOSCDIV1(_SOSCDIV1);
}

void soscMon() { SCG->SOSCCSR |= SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK; }
void soscMon() { SCG->SOSCCSR = SCG->SOSCCSR | (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); }

bool isSoscSysClk() { return (SCG->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0; }

Expand All @@ -332,7 +332,7 @@ void configurPll()
disablePeripheralClocks();

// legacy
RCM->SRIE |= static_cast<uint32_t>(0x8f);
RCM->SRIE = RCM->SRIE | static_cast<uint32_t>(0x8f);
RCM->SSRS = static_cast<uint32_t>(0x1c);

bool sircNeedsConfig = true;
Expand Down
4 changes: 2 additions & 2 deletions platforms/s32k1xx/bsp/bspFlexCan/include/can/FlexCANDevice.h
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Original file line number Diff line number Diff line change
Expand Up @@ -133,12 +133,12 @@ class FlexCANDevice
void enableTransmitInterrupt()
{
fpDevice->IFLAG1 = fTxInterruptMask0;
fpDevice->IMASK1 |= fTxInterruptMask0;
fpDevice->IMASK1 = fpDevice->IMASK1 | fTxInterruptMask0;
}

void disableTransmitInterrupt()
{
fpDevice->IMASK1 &= ~fTxInterruptMask0;
fpDevice->IMASK1 = fpDevice->IMASK1 & ~fTxInterruptMask0;
fpDevice->IFLAG1 = fTxInterruptMask0;
}

Expand Down
16 changes: 8 additions & 8 deletions platforms/s32k1xx/bsp/bspFlexCan/src/can/FlexCANDevice.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -101,10 +101,10 @@ ICanTransceiver::ErrorCode FlexCANDevice::init()
fPhy.init(fConfig.BusId);

// Enable module
fpDevice->MCR &= ~FLEXCAN_MCR_MDIS_MASK;
fpDevice->MCR = fpDevice->MCR & ~FLEXCAN_MCR_MDIS_MASK;

// Soft reset
fpDevice->MCR |= FLEXCAN_MCR_SOFTRST_MASK;
fpDevice->MCR = fpDevice->MCR | FLEXCAN_MCR_SOFTRST_MASK;
if (::bsp::isEqualAfterTimeout<vuint32_t>(
&fpDevice->MCR,
FLEXCAN_MCR_SOFTRST_MASK,
Expand All @@ -115,7 +115,7 @@ ICanTransceiver::ErrorCode FlexCANDevice::init()
}

// Enter freeze mode
fpDevice->MCR |= (FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK);
fpDevice->MCR = fpDevice->MCR | (FLEXCAN_MCR_FRZ_MASK | FLEXCAN_MCR_HALT_MASK);
if (::bsp::isEqualAfterTimeout<vuint32_t>(
&fpDevice->MCR, FLEXCAN_MCR_FRZACK_MASK, 0UL, INIT_DELAY_TIMEOUT_US))
{
Expand All @@ -125,14 +125,14 @@ ICanTransceiver::ErrorCode FlexCANDevice::init()
// Setup MCR:
// Disable self reception
// IRQM have to be switched on
fpDevice->MCR
|= (FLEXCAN_MCR_MAXMB(e_TRANSMIT_BUFFER_MAX) | FLEXCAN_MCR_SRXDIS_MASK
fpDevice->MCR = fpDevice->MCR
| (FLEXCAN_MCR_MAXMB(e_TRANSMIT_BUFFER_MAX) | FLEXCAN_MCR_SRXDIS_MASK
| FLEXCAN_MCR_IRMQ_MASK);

// Setup CTRL
fpDevice->CTRL1 = 0;
fpDevice->CTRL1 |= fConfig.clockSetupRegister;
fpDevice->CTRL2 |= FLEXCAN_CTRL2_MRP_MASK;
fpDevice->CTRL1 = fpDevice->CTRL1 | fConfig.clockSetupRegister;
fpDevice->CTRL2 = fpDevice->CTRL2 | FLEXCAN_CTRL2_MRP_MASK;

// Setup message buffers
fRxInterruptMask = 0;
Expand Down Expand Up @@ -182,7 +182,7 @@ ICanTransceiver::ErrorCode FlexCANDevice::start()
fpDevice->IMASK1 = fRxInterruptMask;

// Leave freeze mode
fpDevice->MCR &= (~FLEXCAN_MCR_HALT_MASK & ~FLEXCAN_MCR_FRZ_MASK);
fpDevice->MCR = fpDevice->MCR & (~FLEXCAN_MCR_HALT_MASK & ~FLEXCAN_MCR_FRZ_MASK);
if (::bsp::isEqualAfterTimeout<vuint32_t>(
&fpDevice->MCR,
(FLEXCAN_MCR_NOTRDY_MASK),
Expand Down
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