Fix code formatting for 'C++20 support'

Signed-off-by: Thomas Frank <thomas.frank@esrlabs.com>
eclipse-openbsw · Nov 25, 2024 · 4837173 · 4837173
1 parent 1612d9b
commit 4837173
Showing 6 changed files with 21 additions and 15 deletions.
diff --git a/...es/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/SystemTimer/SystemTimer.cpp b/...es/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/SystemTimer/SystemTimer.cpp
@@ -52,9 +52,9 @@ void initSystemTimer()
     LPIT0->TMR[0].TVAL  = 0xFFFFFFFFU;
     LPIT0->SETTEN       = 0x1U;
 
-    DEMCR = DEMCR | 0x01000000U;
+    DEMCR      = DEMCR | 0x01000000U;
     DWT_CYCCNT = 0;
-    DWT_CTRL = DWT_CTRL | 0x00000001U;
+    DWT_CTRL   = DWT_CTRL | 0x00000001U;
 
     state.ticks         = 0; // General ticks counter, never overflows
     state.lastDwt       = 0;

diff --git a/executables/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/adc/AnalogInput.cpp b/executables/referenceApp/platforms/s32k148evb/bspConfiguration/src/bsp/adc/AnalogInput.cpp
@@ -32,7 +32,7 @@ void AnalogInput::init()
             sizeof(analogInputScaleConfiguration) / sizeof(AnalogInputScale::scale)),
         &analogInputScaleConfiguration[0]);
 
-    SIM->ADCOPT = 0U;
+    SIM->ADCOPT  = 0U;
     SIM->CHIPCTL = SIM->CHIPCTL & ~SIM_CHIPCTL_PDB_BB_SEL_MASK;
 
     (void)fAdc0.init();

diff --git a/platforms/s32k1xx/bsp/bspClock/src/clockConfig.cpp b/platforms/s32k1xx/bsp/bspClock/src/clockConfig.cpp
@@ -131,8 +131,8 @@ void enablePeripheralClocks(void)
     PCC->PCCn[PCC_FTM2_INDEX] = CLOCK_SOURCE_FTM2;
     PCC->PCCn[PCC_FTM2_INDEX] = PCC->PCCn[PCC_FTM2_INDEX] | 0xC0000000U;
 #endif
-    PCC->PCCn[PCC_ADC0_INDEX] = CLOCK_SOURCE_ADC0;
-    PCC->PCCn[PCC_ADC0_INDEX] = PCC->PCCn[PCC_ADC0_INDEX] | 0xC0000000U;
+    PCC->PCCn[PCC_ADC0_INDEX]   = CLOCK_SOURCE_ADC0;
+    PCC->PCCn[PCC_ADC0_INDEX]   = PCC->PCCn[PCC_ADC0_INDEX] | 0xC0000000U;
     PCC->PCCn[PCC_RTC_INDEX]    = 0xC0000000U;
     PCC->PCCn[PCC_LPTMR0_INDEX] = CLOCK_SOURCE_LPTMR0;
     PCC->PCCn[PCC_LPTMR0_INDEX] = PCC->PCCn[PCC_LPTMR0_INDEX] | 0xC0000000U;
@@ -146,8 +146,8 @@ void enablePeripheralClocks(void)
 #ifdef PCC_EWM_INDEX
     PCC->PCCn[PCC_EWM_INDEX] = 0xC0000000U;
 #endif
-    PCC->PCCn[PCC_LPI2C0_INDEX] = CLOCK_SOURCE_LPI2C0;
-    PCC->PCCn[PCC_LPI2C0_INDEX] = PCC->PCCn[PCC_LPI2C0_INDEX] | 0xC0000000U;
+    PCC->PCCn[PCC_LPI2C0_INDEX]  = CLOCK_SOURCE_LPI2C0;
+    PCC->PCCn[PCC_LPI2C0_INDEX]  = PCC->PCCn[PCC_LPI2C0_INDEX] | 0xC0000000U;
     PCC->PCCn[PCC_LPUART0_INDEX] = CLOCK_SOURCE_LPUART0;
     PCC->PCCn[PCC_LPUART0_INDEX] = PCC->PCCn[PCC_LPUART0_INDEX] | 0xC0000000U;
     PCC->PCCn[PCC_LPUART1_INDEX] = CLOCK_SOURCE_LPUART1;
@@ -279,7 +279,10 @@ void spllSysClk()
     SysTick->LOAD = 80000 - 1;
 }
 
-void spllMon() { SCG->SPLLCSR = SCG->SPLLCSR | (SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK); }
+void spllMon()
+{
+    SCG->SPLLCSR = SCG->SPLLCSR | (SCG_SPLLCSR_SPLLCM_MASK | SCG_SPLLCSR_SPLLCMRE_MASK);
+}
 
 bool isSpllSysClk() { return (SCG->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0; }
 
@@ -309,7 +312,10 @@ void soscConfig()
     SCG->SOSCDIV = SCG_SOSCDIV_SOSCDIV2(_SOSCDIV2) | SCG_SOSCDIV_SOSCDIV1(_SOSCDIV1);
 }
 
-void soscMon() { SCG->SOSCCSR = SCG->SOSCCSR | (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); }
+void soscMon()
+{
+    SCG->SOSCCSR = SCG->SOSCCSR | (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK);
+}
 
 bool isSoscSysClk() { return (SCG->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0; }
 

diff --git a/platforms/s32k1xx/bsp/bspFlexCan/src/can/FlexCANDevice.cpp b/platforms/s32k1xx/bsp/bspFlexCan/src/can/FlexCANDevice.cpp
@@ -126,8 +126,8 @@ ICanTransceiver::ErrorCode FlexCANDevice::init()
     // Disable self reception
     // IRQM have to be switched on
     fpDevice->MCR = fpDevice->MCR
-        | (FLEXCAN_MCR_MAXMB(e_TRANSMIT_BUFFER_MAX) | FLEXCAN_MCR_SRXDIS_MASK
-            | FLEXCAN_MCR_IRMQ_MASK);
+                    | (FLEXCAN_MCR_MAXMB(e_TRANSMIT_BUFFER_MAX) | FLEXCAN_MCR_SRXDIS_MASK
+                       | FLEXCAN_MCR_IRMQ_MASK);
 
     // Setup CTRL
     fpDevice->CTRL1 = 0;

diff --git a/platforms/s32k1xx/bsp/bspFtm/include/ftm/Ftm.h b/platforms/s32k1xx/bsp/bspFtm/include/ftm/Ftm.h
@@ -89,7 +89,7 @@ class Ftm
     {
         (void)setup;
 
-        _cfg = cfg;
+        _cfg               = cfg;
         _ftm.MODE          = _ftm.MODE | FTM_MODE_WPDIS_MASK;
         _ftm.CNTIN         = _cfg->cntin;
         _ftm.MOD           = _cfg->mod;
@@ -120,7 +120,7 @@ class Ftm
     inline void stop()
     {
         _ftm.MODE = _ftm.MODE | FTM_MODE_WPDIS_MASK;
-        _ftm.SC = 0;
+        _ftm.SC   = 0;
     }
 
     inline void start()

diff --git a/platforms/s32k1xx/bsp/bspIo/src/io/Io.cpp b/platforms/s32k1xx/bsp/bspIo/src/io/Io.cpp
@@ -43,7 +43,7 @@ BspReturnCode Io::setConfiguration(uint16_t io, PinConfiguration const& cfg)
             GPIO_Type* portBase = (GPIO_Type*)(gpioPtrs[cfg.port]);
             PORT_Type* cfgBase  = (PORT_Type*)(gpioPrfCfgPtrs[cfg.port]);
             // disable
-            portBase->PIDR = portBase->PIDR | (1 << cfg.pinNumber); // default High-Z
+            portBase->PIDR      = portBase->PIDR | (1 << cfg.pinNumber); // default High-Z
             if (_IN == cfg.dir)
             {
                 // filter settings ..
@@ -184,7 +184,7 @@ bsp::BspReturnCode Io::resetConfig(uint16_t io)
         // disable
         portBase->PIDR = portBase->PIDR | (1 << fPinConfiguration[io].pinNumber); // default High-Z
         portBase->PDDR = portBase->PDDR & ~(1 << fPinConfiguration[io].pinNumber);
-        cfgBase->DFER = cfgBase->DFER & ~(1 << fPinConfiguration[io].pinNumber);
+        cfgBase->DFER  = cfgBase->DFER & ~(1 << fPinConfiguration[io].pinNumber);
         cfgBase->PCR[fPinConfiguration[io].pinNumber] = 0;
         return BSP_OK;
     }