[NoMerge] Pending PRs for T1 Tile

src/main/scala/devices/tilelink/CLINT.scala

@@ -105,7 +105,7 @@ trait CanHavePeripheryCLINT { this: BaseSubsystem =>
   val (clintOpt, clintDomainOpt, clintTickOpt) = p(CLINTKey).map { params =>
     val tlbus = locateTLBusWrapper(p(CLINTAttachKey).slaveWhere)
     val clintDomainWrapper = tlbus.generateSynchronousDomain.suggestName("clint_domain")
-    val clint = clintDomainWrapper { LazyModule(new CLINT(params, cbus.beatBytes)) }
+    val clint = clintDomainWrapper { LazyModule(new CLINT(params, tlbus.beatBytes)) }
     clintDomainWrapper { clint.node := tlbus.coupleTo("clint") { TLFragmenter(tlbus) := _ } }
     val clintTick = clintDomainWrapper { InModuleBody {
       val tick = IO(Input(Bool()))

src/main/scala/groundtest/GroundTestSubsystem.scala

@@ -21,8 +21,8 @@ class GroundTestSubsystem(implicit p: Parameters)
   with HasTileInputConstants
   with CanHaveMasterAXI4MemPort
 {
-  val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=pbus.beatBytes))
-  pbus.coupleTo("TestRAM") { testram.node := TLFragmenter(pbus) := _ }
+  val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), beatBytes=tlBusWrapperLocationMap.get(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).beatBytes))
+  tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))).coupleTo("TestRAM") { testram.node := TLFragmenter(tlBusWrapperLocationMap.lift(PBUS).getOrElse(tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))))) := _ }
 
   // No cores to monitor
   def coreMonitorBundles = Nil

src/main/scala/subsystem/BaseSubsystem.scala

@@ -78,11 +78,12 @@ trait HasConfigurableTLNetworkTopology { this: HasTileLinkLocations =>
 
   // Calling these functions populates tlBusWrapperLocationMap and connects the locations to each other.
   val topology = p(TLNetworkTopologyLocated(location))
-  topology.map(_.instantiate(this))
+  topology.foreach(_.instantiate(this))
   topology.foreach(_.connect(this))
+  def viewpointBus: TLBusWrapper = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))
 
   // This is used lazily at DTS binding time to get a view of the network
-  lazy val topManagers = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))).unifyManagers
+  lazy val topManagers = viewpointBus.unifyManagers
 }
 
 /** Base Subsystem class with no peripheral devices, ports or cores added yet */
@@ -98,18 +99,11 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
 
   val busContextName = "subsystem"
 
-  val sbus = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))
-  tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := allClockGroupsNode }
+  viewpointBus.clockGroupNode := allClockGroupsNode
 
   // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding
-  // a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.
-  ibus.clockNode := sbus.fixedClockNode
-
-  // TODO deprecate these public members to see where users are manually hardcoding a particular bus that might actually not exist in a certain dynamic topology
-  val pbus = tlBusWrapperLocationMap.lift(PBUS).getOrElse(sbus)
-  val fbus = tlBusWrapperLocationMap.lift(FBUS).getOrElse(sbus)
-  val mbus = tlBusWrapperLocationMap.lift(MBUS).getOrElse(sbus)
-  val cbus = tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus)
+  //       a PLIC to the CBUS, ensure it is synchronously coupled to the SBUS.
+  ibus.clockNode := viewpointBus.fixedClockNode
 
   // Collect information for use in DTS
   ResourceBinding {
@@ -150,7 +144,7 @@ abstract class BaseSubsystemModuleImp[+L <: BaseSubsystem](_outer: L) extends Ba
   Annotated.addressMapping(this, mapping)
 
   println("Generated Address Map")
-  mapping.map(entry => println(entry.toString((dtsLM.sbus.busView.bundle.addressBits-1)/4 + 1)))
+  mapping.foreach(entry => println(entry.toString((dtsLM.tlBusWrapperLocationMap(p(TLManagerViewpointLocated(dtsLM.location))).busView.bundle.addressBits-1)/4 + 1)))
   println("")
 
   ElaborationArtefacts.add("memmap.json", s"""{"mapping":[${mapping.map(_.toJSON).mkString(",")}]}""")

src/main/scala/subsystem/Ports.scala

@@ -36,6 +36,7 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem =>
   private val portName = "axi4"
   private val device = new MemoryDevice
   private val idBits = memPortParamsOpt.map(_.master.idBits).getOrElse(1)
+  private val mbus = tlBusWrapperLocationMap.get(MBUS).getOrElse(viewpointBus)
 
   val memAXI4Node = AXI4SlaveNode(memPortParamsOpt.map({ case MemoryPortParams(memPortParams, nMemoryChannels, _) =>
     Seq.tabulate(nMemoryChannels) { channel =>
@@ -63,17 +64,17 @@ trait CanHaveMasterAXI4MemPort { this: BaseSubsystem =>
       memPortParams.incohBase.foreach(incohBase => {
         val cohRegion = AddressSet(0, incohBase-1)
         val incohRegion = AddressSet(incohBase, incohBase-1)
-        val replicator = sbus {
+        val replicator = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location))) {
           val replicator = LazyModule(new RegionReplicator(ReplicatedRegion(cohRegion, cohRegion.widen(incohBase))))
           val prefixSource = BundleBridgeSource[UInt](() => UInt(1.W))
           replicator.prefix := prefixSource
           // prefix is unused for TL uncached, so this is ok
           InModuleBody { prefixSource.bundle := 0.U(1.W) }
           replicator
         }
-        sbus.coupleTo(s"memory_controller_bypass_port_named_$portName") {
+        viewpointBus.coupleTo(s"memory_controller_bypass_port_named_$portName") {
           (mbus.crossIn(mem_bypass_xbar)(ValName("bus_xing"))(p(SbusToMbusXTypeKey))
-            := TLWidthWidget(sbus.beatBytes)
+            := TLWidthWidget(viewpointBus.beatBytes)
             := replicator.node
             := TLFilter(TLFilter.mSubtract(cohRegion))
             := TLFilter(TLFilter.mResourceRemover)
@@ -116,14 +117,14 @@ trait CanHaveMasterAXI4MMIOPort { this: BaseSubsystem =>
         beatBytes = params.beatBytes)).toSeq)
 
   mmioPortParamsOpt.map { params =>
-    sbus.coupleTo(s"port_named_$portName") {
+    viewpointBus.coupleTo(s"port_named_$portName") {
       (mmioAXI4Node
         := AXI4Buffer()
         := AXI4UserYanker()
-        := AXI4Deinterleaver(sbus.blockBytes)
+        := AXI4Deinterleaver(viewpointBus.blockBytes)
         := AXI4IdIndexer(params.idBits)
         := TLToAXI4()
-        := TLWidthWidget(sbus.beatBytes)
+        := TLWidthWidget(viewpointBus.beatBytes)
         := _)
     }
   }
@@ -136,6 +137,7 @@ trait CanHaveSlaveAXI4Port { this: BaseSubsystem =>
   private val slavePortParamsOpt = p(ExtIn)
   private val portName = "slave_port_axi4"
   private val fifoBits = 1
+  private val fbus = tlBusWrapperLocationMap.get(FBUS).getOrElse(viewpointBus)
 
   val l2FrontendAXI4Node = AXI4MasterNode(
     slavePortParamsOpt.map(params =>
@@ -174,17 +176,17 @@ trait CanHaveMasterTLMMIOPort { this: BaseSubsystem =>
           address            = AddressSet.misaligned(params.base, params.size),
           resources          = device.ranges,
           executable         = params.executable,
-          supportsGet        = TransferSizes(1, sbus.blockBytes),
-          supportsPutFull    = TransferSizes(1, sbus.blockBytes),
-          supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
+          supportsGet        = TransferSizes(1, viewpointBus.blockBytes),
+          supportsPutFull    = TransferSizes(1, viewpointBus.blockBytes),
+          supportsPutPartial = TransferSizes(1, viewpointBus.blockBytes))),
         beatBytes = params.beatBytes)).toSeq)
 
   mmioPortParamsOpt.map { params =>
-    sbus.coupleTo(s"port_named_$portName") {
+    viewpointBus.coupleTo(s"port_named_$portName") {
       (mmioTLNode
         := TLBuffer()
         := TLSourceShrinker(1 << params.idBits)
-        := TLWidthWidget(sbus.beatBytes)
+        := TLWidthWidget(viewpointBus.beatBytes)
         := _ )
     }
   }
@@ -210,7 +212,7 @@ trait CanHaveSlaveTLPort { this: BaseSubsystem =>
           sourceId = IdRange(0, 1 << params.idBits))))).toSeq)
 
   slavePortParamsOpt.map { params =>
-    sbus.coupleFrom(s"port_named_$portName") {
+    viewpointBus.coupleFrom(s"port_named_$portName") {
       ( _
         := TLSourceShrinker(1 << params.sourceBits)
         := TLWidthWidget(params.beatBytes)