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Update ECC SRAM to improve throughput on full write #3557

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merged 1 commit into from
Jan 18, 2024

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Kevin99214
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Type of change: feature request

Impact: no functional change

Development Phase: implementation

Release Notes
Enhance ECC SRAM write throughput when eccBytes > 1 by 2 cycles per write when utilizing the full bus.

Change a_sublane to also check the mask to see if the transaction a partial write. Improves throughput in cases when the full bus is being utilized
@Kevin99214 Kevin99214 changed the title Update SRAM to improve throughput on full write Update ECC SRAM to improve throughput on full write Jan 16, 2024
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@jerryz123 jerryz123 left a comment

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Thanks!

@jerryz123 jerryz123 merged commit 2fd1d1f into chipsalliance:master Jan 18, 2024
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2 participants