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Remove Scalar Crypto and BitManip (copy #3532) #3541

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merged 1 commit into from
Nov 25, 2023
Merged

Remove Scalar Crypto and BitManip (copy #3532) #3541

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2 changes: 1 addition & 1 deletion .github/workflows/mill-ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ jobs:
if: ${{ false }} # disable for now, I prefer adding firesim-based simulation framework in the future.
strategy:
matrix:
config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei", "BitManipCryptoConfig,64,RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh", "BitManipCrypto32Config,32,RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"]
config: ["DefaultRV32Config,32,RV32IMACZicsr_Zifencei", "DefaultConfig,64,RV64IMACZicsr_Zifencei"]
steps:
- uses: actions/checkout@v2
with:
Expand Down
7 changes: 1 addition & 6 deletions build.sc
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Original file line number Diff line number Diff line change
Expand Up @@ -185,7 +185,7 @@ trait Emulator extends Cross.Module2[String, String] {
"debug_rob.cc",
"emulator.cc",
"remote_bitbang.cc",
).map(c => PathRef(csrcDir().path / c))
).map(c => PathRef(csrcDir().path / c))
}

def CMakeListsString = T {
Expand Down Expand Up @@ -295,8 +295,6 @@ object emulator extends Cross[Emulator](
//
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
)

object `runnable-riscv-test` extends mill.Cross[RiscvTest](
Expand Down Expand Up @@ -384,9 +382,6 @@ object `runnable-arch-test` extends mill.Cross[ArchTest](
// For CI within reasonable time
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "64", "RV64IMACZicsr_Zifencei"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config", "32", "RV32IMACZicsr_Zifencei"),

("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig", "64", "RV64IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config", "32", "RV32IZba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh_Zksed_Zksh"),
)

object `runnable-jtag-dtm-test` extends mill.Cross[JTAGDTMTest](
Expand Down
24 changes: 0 additions & 24 deletions scripts/arch-test/emulator/riscof_emulator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml):
self.isa += '_Zicsr'
if "Zifencei" in ispec["ISA"]:
self.isa += '_Zifencei'
if "Zba" in ispec["ISA"]:
self.isa += '_Zba'
if "Zbb" in ispec["ISA"]:
self.isa += '_Zbb'
if "Zbc" in ispec["ISA"]:
self.isa += '_Zbc'
if "Zbkb" in ispec["ISA"]:
self.isa += '_Zbkb'
if "Zbkc" in ispec["ISA"]:
self.isa += '_Zbkc'
if "Zbkx" in ispec["ISA"]:
self.isa += '_Zbkx'
if "Zbs" in ispec["ISA"]:
self.isa += '_Zbs'
if "Zknd" in ispec["ISA"]:
self.isa += '_Zknd'
if "Zkne" in ispec["ISA"]:
self.isa += '_Zkne'
if "Zknh" in ispec["ISA"]:
self.isa += '_Zknh'
if "Zksed" in ispec["ISA"]:
self.isa += '_Zksed'
if "Zksh" in ispec["ISA"]:
self.isa += '_Zksh'

#TODO: The following assumes you are using the riscv-gcc toolchain. If
# not please change appropriately
Expand Down
24 changes: 0 additions & 24 deletions scripts/arch-test/spike/riscof_spike.py
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Original file line number Diff line number Diff line change
Expand Up @@ -111,30 +111,6 @@ def build(self, isa_yaml, platform_yaml):
self.isa += '_Zicsr'
if "Zifencei" in ispec["ISA"]:
self.isa += '_Zifencei'
if "Zba" in ispec["ISA"]:
self.isa += '_Zba'
if "Zbb" in ispec["ISA"]:
self.isa += '_Zbb'
if "Zbc" in ispec["ISA"]:
self.isa += '_Zbc'
if "Zbkb" in ispec["ISA"]:
self.isa += '_Zbkb'
if "Zbkc" in ispec["ISA"]:
self.isa += '_Zbkc'
if "Zbkx" in ispec["ISA"]:
self.isa += '_Zbkx'
if "Zbs" in ispec["ISA"]:
self.isa += '_Zbs'
if "Zknd" in ispec["ISA"]:
self.isa += '_Zknd'
if "Zkne" in ispec["ISA"]:
self.isa += '_Zkne'
if "Zknh" in ispec["ISA"]:
self.isa += '_Zknh'
if "Zksed" in ispec["ISA"]:
self.isa += '_Zksed'
if "Zksh" in ispec["ISA"]:
self.isa += '_Zksh'

#TODO: The following assumes you are using the riscv-gcc toolchain. If
# not please change appropriately
Expand Down
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