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Support vector-units w/o L1D$ access (copy #3537) #3540

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merged 4 commits into from
Jan 4, 2024
Merged

Support vector-units w/o L1D$ access (copy #3537) #3540

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9c35f3b
remove vMemDataBits check
sequencer Nov 23, 2023
e9ed56f
remove vector on dcache port
sequencer Nov 23, 2023
ed7e6f7
add vectorUseDCache parameter
sequencer Nov 25, 2023
2813aab
Merge branch 'master' into mergify/copy/master/pr-3537
jerryz123 Dec 28, 2023
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2 changes: 1 addition & 1 deletion src/main/scala/tile/BaseTile.scala
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Expand Up @@ -93,7 +93,7 @@ trait HasNonDiplomaticTileParameters {

// TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks
// Core PTW DTIM coprocessors
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + tileParams.core.useVector.toInt
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt

// TODO merge with isaString in CSR.scala
def isaDTS: String = {
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2 changes: 1 addition & 1 deletion src/main/scala/tile/Core.scala
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Expand Up @@ -23,6 +23,7 @@ trait CoreParams {
val useAtomicsOnlyForIO: Boolean
val useCompressed: Boolean
val useVector: Boolean = false
val vectorUseDCache: Boolean = false
val useRVE: Boolean
val useConditionalZero: Boolean
val mulDiv: Option[MulDivParams]
Expand Down Expand Up @@ -113,7 +114,6 @@ trait HasCoreParameters extends HasTileParameters {
if (usingVector) {
require(isPow2(vLen), s"vLen ($vLen) must be a power of 2")
require(eLen >= 32 && vLen % eLen == 0, s"eLen must divide vLen ($vLen) and be no less than 32")
require(vMemDataBits >= eLen && vLen % vMemDataBits == 0, s"vMemDataBits ($vMemDataBits) must divide vLen ($vLen) and be no less than eLen ($eLen)")
}

lazy val hartIdLen: Int = p(MaxHartIdBits)
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