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Fence for RoCC on rocc-csr writes #3539

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merged 2 commits into from
Feb 12, 2024
Merged

Fence for RoCC on rocc-csr writes #3539

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52b8c6e
Fence for RoCC on rocc-csr writes
jerryz123 Nov 25, 2023
dfaa357
Simplify id_csr_rocc_write
jerryz123 Feb 2, 2024
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3 changes: 2 additions & 1 deletion src/main/scala/rocket/RocketCore.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -349,7 +349,8 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
val id_rocc_busy = usingRoCC.B &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_do_fence = WireDefault(id_rocc_busy && id_ctrl.fence ||
val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren
val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))

val bpu = Module(new BreakpointUnit(nBreakpoints))
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