Fix FP16 for XLEN64

chipsalliance · Jul 26, 2024 · f2093af · f2093af
1 parent e53bbfc
commit f2093af
Showing 1 changed file with 1 addition and 2 deletions.
diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
@@ -472,8 +472,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetime
   dcmp.io.signaling := !in.rm(1)
 
   val tag = in.typeTagOut
-  val store = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen,   ieee(in.in1)(15, 0).sextTo(minXLen))
-                                   else              Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
+  val store = (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
 
   val toint = WireDefault(store)
   val intType = WireDefault(in.fmt(0))