Add pgLevels check to Tile

chipsalliance · Jun 30, 2024 · 4b80c37 · 4b80c37
1 parent e3da6bd
commit 4b80c37
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
@@ -121,6 +121,14 @@ trait HasCoreParameters extends HasTileParameters {
     require(vfLen <= eLen)
   }
 
+  if (coreParams.useVM) {
+    if (coreParams.xLen == 32) {
+      require(coreParams.pgLevels == 2)
+    } else {
+      require(coreParams.pgLevels >= 3)
+    }
+  }
+
   lazy val hartIdLen: Int = p(MaxHartIdBits)
   lazy val resetVectorLen: Int = {
     val externalLen = paddrBits