Remove old sbus arg to CoherentBusTopoParams

chipsalliance · Feb 1, 2023 · 2e9077c · 2e9077c
1 parent ba35010
commit 2e9077c
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala
@@ -89,15 +89,14 @@ case class HierarchicalBusTopologyParams(
 
 /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */
 case class CoherentBusTopologyParams(
-  sbus: SystemBusParams, // TODO remove this after better width propagation
   mbus: MemoryBusParams,
   coherence: BankedCoherenceParams,
   sbusToMbusXType: ClockCrossingType = NoCrossing,
   driveMBusClockFromSBus: Boolean = true
 ) extends TLBusWrapperTopology(
   instantiations = (if (coherence.nBanks == 0) Nil else List(
     (MBUS, mbus),
-    (COH, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, coherence.nBanks, COH.name, sbus.dtsFrequency)(coherence.coherenceManager)))),
+    (COH, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, coherence.nBanks, COH.name)(coherence.coherenceManager)))),
   connections = if (coherence.nBanks == 0) Nil else List(
     (SBUS, COH,   TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
     (COH,  MBUS,  TLBusWrapperConnection.crossTo(
@@ -117,3 +116,4 @@ case class ClusterBusTopologyParams(
     (CBUS, ccbus)),
   connections = Nil
 )
+
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -82,7 +82,6 @@ class WithCoherentBusTopology extends Config((site, here, up) => {
         fbusToSbusXType = site(FbusToSbusXTypeKey)),
       driveClocksFromSBus = site(DriveClocksFromSBus)),
     CoherentBusTopologyParams(
-      sbus = site(SystemBusKey),
       mbus = site(MemoryBusKey),
       coherence = site(BankedCoherenceKey),
       sbusToMbusXType = site(SbusToMbusXTypeKey),