Support vector-units w/o L1D$ access #784

Job	Run time
riscv-arch-test	0s
riscv-tests (DefaultConfig)	19m 32s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultC...	21m 35s
riscv-tests (DefaultBufferlessConfig)	19m 39s
emulator (DefaultSmallConfig)	12m 58s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultR...	20m 1s
riscv-tests (DefaultRV32Config)	19m 48s
emulator (DualBankConfig)	13m 21s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebu...	18m 28s
riscv-tests (TinyConfig)	13m 36s
emulator (DualChannelConfig)	13m 36s
jtag-dtm-test (freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebu...	17m 11s
riscv-tests (DefaultFP16Config)	13m 59s
emulator (DualChannelDualBankConfig)	13m 35s
emulator (RoccExampleConfig)	13m 5s
emulator (Edge128BitConfig)	13m 34s
emulator (Edge32BitConfig)	13m 28s
emulator (QuadChannelBenchmarkConfig)	13m 37s
emulator (EightChannelConfig)	13m 25s
emulator (DualCoreConfig)	13m 46s
emulator (MemPortOnlyConfig)	12m 58s
emulator (MMIOPortOnlyConfig)	12m 44s
emulator (CloneTileConfig)	14m 16s
emulator (HypervisorConfig)	13m 4s
	5h 51m 16s

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